TMPR4937 datasheet(266/552 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-8

Configuration cycles will be accepted as the target only when in the Satellite mode. After reset,

Retry response to PCI Configuration access will continue until the software sets the Target

Configuration Access Ready Bit (PCICFG.TCAR) of the PCI Controller Configuration Register.

Please use the software to set this bit after the software initialization process ends and the software

is ready to accept PCI configuration.

•

Interrupt Acknowledge

This command issues interrupt acknowledge cycles as an initiator only when in the Host mode.

Interrupt acknowledge cycles are executed on the PCI Bus when the G2P Interrupt Acknowledge

Data Register (G2PINTACK) is read. The value returned by this Read becomes the interrupt

acknowledge cycle data.

The TX4937 does not support interrupt acknowledge cycles as the target.

•

Special Cycle

This command issues specialy cycles as the initiator only when in the Host mode. This

command issues special cycles on the PCI Bus when writing to the G2P Special Cycle Data

The TX4937 does not support special cycles as the target.

10.3.4 Initiator Access (G-Bus

→ PCI Bus Address Conversion)

During PCI initiator access, the G-Bus address of the Burst transaction issued by the G-Bus that was

converted into the PCI Bus address is used to issue a Burst transaction on the PCI Bus. 36-bit physical

address (G-Bus addresses) are used on the G-Bus. Also, 40-bit PCI Bus addresses are used on the PCI

Bus.

Three memory access windows and one I/O access window can be set in the G-Bus space (Figure

10.3.3). The size of each window is variable. When Burst transactions are issued to these access

windows on the G-Bus, then that G-Bus address is converted into a PCI Bus address that is used to issue

a Burst transaction to the PCI Bus as the initiator. PCI memory access is issued when the access

window is the memory access window. PCI I/O access is issued when the access window is the I/O

access window. Dual access cycles are also issued to the PCI Bus when the PCI Bus address exceeds

0x00_FFFF_FFFF.

Figure 10.3.3 Initiator Access Memory Window

0x00_0000_0000

0xFF_FFFF_FFFF

0x0_0000_0000

0x00_0000_0000

0xFF_FFFF_FFFF

0xF_FFFF_FFFF

PCI I/O Space

G-Bus Space

PCI Memory Space

Memory Access Window

I/O Access Window

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