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TMPR4937 bảng dữ liệu(PDF) 262 Page - Toshiba Semiconductor |
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TMPR4937 bảng dữ liệu(HTML) 262 Page - Toshiba Semiconductor |
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262 / 552 page ![]() Chapter 10 PCI Controller 10-4 10.3 Detailed Explanation 10.3.1 Terminology Explanation The following terms are used in this chapter. • Initiator Means the bus Master of the PCI Bus. The TX4937 operates as the initiator when it obtains the PCI Bus and issues PCI access. • Target Means the bus Slave of the PCI Bus. The TX4937 operates as the target when an external PCI device on the PCI Bus executes PCI access to the TX4937. • Host mode One PCI Host device exists for one PCI Bus. The PCI Host device uses a PCI configuration space to perform PCI configuration on other PCI devices on the PCI Bus. The TX4937 is set to the Host mode if the ADDR[19] signal is High when the RESET* signal is being deasserted. • Satellite mode A PCI device other than the PCI Host device accepts configuration from the PCI Host device. This state is referred to as the Satellite mode. The TX4937 is set to the Satellite mode if the ADDR[19] signal is Low when the RESET signal is being deasserted. • DWORD, QWORD DWORD expresses 32-bit words, and QWORD expresses 64-bit words. According to conventions observed regarding MIPS architecture, this manual uses the following expressions: Byte: 8-bit Half-word: 16-bit Word: 32-bit Double-word: 64-bit 10.3.2 On-chip Register The PCI Controller on-chip register contains the PCI Configuration Space Register and the PCI Controller Control Register. The registers that can be accessed vary according to whether the current mode is the Host mode or the Satellite mode. An external PCI Host device only accesses the PCI Configuration Space Register when in the Satellite mode. This register is defined in the PCI Bus Specifications. A PCI configuration cycle is used to access this register. This register cannot be accessed when in the Host mode. Section “10.5 PCI Configuration Space Register” explains each register in detail. The PCI Controller Control Register is only accessed by the TX49 core and cannot be accessed from the PCI Bus. |
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