TMPR4937 datasheet(259/552 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-1

10. PCI Controller

10.1 Features

The TX4937 PCI Controller functions as a bus bridge between the TX4937 External PCI and the internal

bus (G-Bus).

10.1.1 Overall

•

Compliant to “PCI Local Bus Specification Revision 2.2”

•

PCI Bus: 32-bit data bus; Internal Bus: 64-bit data bus

•

Maximum PCI bus clock operating frequency: 66 MHz

•

Dual address cycle support (40-bit PCI address space)

•

Supports both the Initiator and Target functions

•

Supports power management functions that are compliant to PCI Bus Power Management Interface

Specifications Version 1.1.

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On-chip PCI Bus Arbiter, can connect to a maximum of four external bus masters

•

1-channel on-chip DMA Controller (PDMAC) dedicated to the PCI Controller

•

Supports six PCI clock outputs

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The Internal Bus clock and PCI Bus clock are asynchronous and can be set independently

•

Includes function for booting the TX4937 from memory on the PCI Bus

•

Can set configuration data from serial ROM

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Mounted a retry function on the Internal Bus side also in order to avoid deadlock on the PCI Bus.

10.1.2 Initiator Function

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Single and Burst transfer from the Internal Bus to the PCI Bus

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Supports memory, I/O, configuration, special cycle, and interrupt acknowledge transactions.

•

Address mapping between the Internal Bus and the PCI Bus can be modified

•

Mounted 8-stage 64-bit data one FIFO each for Read and Write

•

Post Write function enables quick termination of a maximum of four Write transactions by the G-

Bus without waiting for completion on the PCI Bus.

•

Endian switching function

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