TMPR4937 datasheet(415/552 Pages) TOSHIBA

415 / 552 page

Chapter 14 AC-link Controller

14-9

14.3.6 Sample-data Transmission and Reception

This section describes the mechanism for transmission and reception of PCM audio and modem

wave-data. An overview is described first. The DMA (Direct Memory Access) operation, error

detection and recovery procedure follow. A special case using slot activation control is described last.

14.3.6.1 Overview

Figure 14.3.6 and Figure 14.3.7 show conceptual views of the sample-data transmission and

reception mechanisms.

Figure 14.3.6 Sample-data Transmission Mechanism

Figure 14.3.7 Sample-data Reception Mechanism

The CODEC requests ACLC to transmit and receive sample-data via ‘slot-request’ and ‘slot-

valid’ bit-fields on the SDIN signal of AC-link.

For transmission, ACLC transmits the data with ‘slot-valid’ tag set. For reception, ACLC

captures the slot-data.

Transmission or reception through each stream can be independently activated or deactivated

under control of ACLC Slot Enable Register (ACSLTEN).

ACLC is equipped with a separate FIFO for each data-stream.

The data to transmit is

prefetched from memory to FIFO through DMA. The received data is buffered on FIFO and then

stored to memory through DMA.

In this stage, each DMA is independently activated or

deactivated under control of ACLC Control Enable Register (ACCTLEN).

DMAC

FIFO

DMA

Buffer

Memory

Read

Data

DMAREQ

Write

Data

ACCTLEN

REQ

Latch

Strobe

ACSLTEN

Valid Flag

Data

Link-

side

Slot Req

Slot Valid,

Slot Data

AC-link

Underrun Error

ACLC

DMAC

FIFO

DMA

Buffer

Memory

Write

Data

DMAREQ

Read

Data

ACCTLEN

REQ

Latch

Strobe

ACSLTEN

Data

Link-

side

Slot Valid,

Slot Data

AC-link

Overrun Error

ACLC

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