TMPR4937 datasheet(413/552 Pages) TOSHIBA

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Chapter 14 AC-link Controller

14-7

14.3.4 AC-link Start Up

Figure 14.3.5 shows the conceptual sequence of AC-link start-up.

The ACLC Control Enable Register’s Enable AC-link bit is used to deassert/assert the ACRESET*

signal to the link side (including AC-link). This bit defaults to ‘0’, so the CPU asserts the ACRESET*

signal when it boots up.

The AC’97 specification requires that the reset assertion period is 1

µs or longer. The software is

responsible for controlling the length of this period.

The AC’97 specification also requires that the primary CODEC stops the AC-link clock (BITCLK)

signal during the period from ACRESET* signal assertion to 162.8ns after ACRESET* signal

deassertion. ACLC assumes the primary CODEC meet this requirement.

Deasserting the link-side reset makes the primary CODEC start driving the BITCLK signal. When

the BITCLK signal is provided, ACLC starts the SYNC signal output, which indicates the start of the

AC-link frame, and starts the frame-length counting.

When a CODEC becomes ready to receive access to its own register, the CODEC sets the “CODEC

Ready” bit of the Tag slot. When ACLC detects that this bit has been set, the ACLC Interrupt Status

able to recognize the readiness of the CODEC(s) by detecting this event by way of either polling or

interrupt.

In case of 5.1 channel audio connection example (Figure 14.3.2), because the secondary CODEC is

connected to the SDIN1 signal of ACLC, the software must watch ACINTSTS.CODEC1RDY bit to

determine the CODEC’s readiness for the register access.

Figure 14.3.5 Cold Reset and CODEC Ready Recognition

SDIN

ACRESET*

BITCLK

SYNC

ENLINK

CODECRDY

ACLC internal clock becomes active

Software sets ENLINK bit

CODEC becomes ready to accept register access

Boot up

Note: The number of BITCLK cycles relative to other signals is not to scale.

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