TMPR4937 datasheet(414/552 Pages) TOSHIBA

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Chapter 14 AC-link Controller

14-8

14.3.5 CODEC Register Access

By accessing registers in the CODEC, the system software is able to detect or control the CODEC

state. This section describes how to read and write CODEC registers via ACLC. For details about

AC’97 register set and proper sequence to operate CODEC, refer to the AC’97 specification and target

CODEC datasheet.

It takes several frame periods for a read or write access to complete. Taking this into account, ACLC

is equipped with a function for reporting CODEC register access completion as status-change or

interrupt.

In order to read an AC’97 register, write the access destination CODEC ID and register address in

ACLC CODEC Register Access Register (ACREGACC) with its CODECRD bit set to “1”. After the

ACLC Interrupt Status Register (ACINTSTS)’s REGACC Ready (REGACCRDY) bit is set, the

software is able to get the data returned from the AC’97 by reading the ACREGACC register and issue

another access.

In order to write to an AC’97 register, write the access destination CODEC ID, register address, and

the data in ACLC’s ACREGACC register with ACREGACC.CODECRD bit set to “0”. After the

ACINTSTS.REGACCRDY bit has been set, the software is able to issue another access.

In case of 5.1 channel audio connection example (Figure 14.3.2), because the secondary CODEC has

CODEC ID of ‘3’, the software must write ‘3’ into ACREGACC.CODECID field when it issues

secondary CODEC register access.

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