TMPR4937 datasheet(354/552 Pages) TOSHIBA

354 / 552 page

Chapter 10 PCI Controller

10-96

Bit

Mnemonic

Field Name

Description

Read/Write

XFRACT

Transfer Active

Transfer Active (Default: 0x0)

This bit is a copy of the Transfer Active bit in the PDMAC Configuration

ACCMP

Abnormal Chain

Completion

Abnormal Chain Complete (Default: 0x0)

1: Indicates that the Chain transfer ended in an error state. In other words,

this reflects an OR operation of the PDMAC Status Register bits [3:0].

0: Indicates that no error has occurred in the Chain transfer since the

previous error bit was cleared.

Note: Bits [3:0] of the PDMAC Status Register must be cleared in order to

clear this bit.

NCCMP

Normal Chain

Completion

Normal Chain Complete (Default: 0x0)

1: Indicates that the Chain transfer ended in the Normal state.

0: Indicates that Chain transfer has not ended since this bit was previously

cleared.

R/W1C

NTCMP

Normal Data

Transfer

Complete

Normal Data Transfer Complete (Default: 0x0)

1: Indicates that the data transfer specified by the PDMAC Register ended

in the Normal state.

0: Indicates that data transfer has not ended since this bit was previously

cleared.

R/W1C

Reserved

⎯

CFGERR

Configuration

Error

Configuration Error (Default: 0x0)

1: Indicates that either the current setting of the control portion in the

Control Register and the Address/Count Register are not consistent with

each other or the PDMAC stipulation is not being obeyed. DMA transfer

stops.

0: Indicates that the current setting of the control portion in the Control

R/W1C

PCIERR

PCI Fatal Error

PCI Fatal Error (Default: 0x0)

1: Indicates that an error was signaled on the PCI Bus during the Chain

process.

0: Indicates that no error has been signaled on the PCI Bus since this bit

was previously cleared.

R/W1C

CHNERR

G-Bus Chain

Error

G-Bus Chain Bus Error (Default: 0x0)

1: Indicates that a G-Bus error occurrred during the Chain process. DMA

transfer stops.

0: Indicates that no G-Bus error has occurred during the Chain process

since this bit was cleared.

R/W1C

DATAERR

G-Bus Data Error G-Bus Data Bus Error (Default: 0x0)

1: Indicates that a G-Bus error occurred during the data transfer process.

DMA transfer stops.

0: Indicates that no G-Bus error has occurred during the data transfer

process since this bit was cleared.

R/W1C

Figure 10.4.61 Status Register (2/2)

TMPR4937 bảng dữ liệu(PDF) 354 Page - Toshiba Semiconductor

TMPR4937 bảng dữ liệu(HTML) 354 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL