TMPR4937 datasheet(352/552 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-94

Bit

Mnemonic

Field Name

Description

Read/Write

NTCMPIE

Normal Data

Transfer Complete

Interrupt Enable

Interrupt Enable on Transfer Done (Default: 0x0)

1: PDMAC generates an interrupt when the current data transfer is

complete.

0: PDMAC does not generate an interrupt when the current data transfer is

complete.

R/W

CHNEN

Chain Enable

Chain Enable (Default: 0x0) (Read Only)

When the current data transfer is complete, this field reads the next data

command Descriptor from the address indicated by the PDMAC Chain

Address Register then indicates whether to continue the transfer or not.

This bit is only set to “1” when either a CPU Write process or a Descriptor

Read process sets a value other than “0” in the PDMAC Chain Address

This bit is cleared to “0” if either the Channel Reset bit is set, or “0” is set in

the PDMAC Chain Address Register by a CPU Write or a Descriptor Read

process.

The above 0 value judgement is not performed when the TX49/H3 core

stores the upper 32 bits in the PDMAC Chain Address Register.

1: Reads the next data command Descriptor.

0: Does not read the next data command Descriptor.

XFRACT

Transfer Active

Transfer Active (Default: 0x0)

Specifies whether to perform DMA transfer or not.

Setting this bit after setting the appropriate value in the register group

initiates DMA data transfer.

This bit is not set if the PDMAC Count Register value is “0” and the Chain

Enable bit is cleared when “1” is written to this bit.

Even when a value other than “0” is written to the Chain Address Register,

“1” is set to this bit and DMA transfer automatically starts.

The above 0 value judgement is not performed when the TX49/H3 core

stores the upper 32 bits in the PDMAC Chain Address Register.

Data transfer will be stopped after a short delay if this bit is cleared while

the data transfer is in progress.

This bit is automatically cleared to “0” either when data transfer ends

normally or is stopped by an error.

Never clear XFRACT by software, because it stops guaranteeing a normal

operation,.

1: Perform data transfer.

0: Do not perform data transfer.

R/W

Reserved

⎯

BSWAP

Byte Swap Within

DWORD

Swap Bytes in DWORD (Default: 0x0)

Specifies whether to perform 32-bit data byte swapping.

Please leave this bit at “0” for normal usage.

Setting this bit when in the Big Endian mode executes data transfer so the

byte order of the 32-bit data on the PCI Bus (which is Little Endian) does

not change.

1: Swap the byte order of each 32-bit DWORD data, then transfer.

0: Transfer without swapping the byte order of each 32-bit DWORD data.

R/W

3:2

XFRSIZE

Transfer Size

Transfer Size (Default: 0x0)

Specifies the data transfer size in one G-Bus transaction on the G-Bus.

00: 1 DWORD (32-bit)

01: 1 QWORD (64-bit)

10: 4 QWORD (Burst transfer)

11: Reserved

R/W

XFRDIRC

Transfer Direction Transfer Direction (Default: 0x0)

Specifies the DMA data transfer direction.

1: Transfers data from the G-Bus to the PCI Bus.

0: Transfers data from the PCI Bus to the G-Bus.

R/W

CHRST

Channel Reset

Channel Reset (Default: 0x1)

Resets the DMA channel.

This bit must be cleared by the software in advance so the channel can

start the data transfer. This reset function is not supported when PDMAC is

in operation.

Ensure that the Transfer Active (XFARCT) bit in the PDMSTATUS register

is cleared prior to resetting the DMA channel. For chained DMA, also

ensure either the Abnormal Chain Complete (ACCMP) or Normal Chain

Complete (NCCMP) bit in the PDMSTATUS register is set.

1: All logic and State Machines are reset.

0: The channel becomes valid.

R/W

Figure 10.4.60 PDMAC Configuration Register (2/2)

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