TMPR4937 datasheet(351/552 Pages) TOSHIBA

351 / 552 page

Chapter 10 PCI Controller

10-93

10.4.62 PDMAC Configuration Register (PDMCFG)0xD220

Reserved

: Type

: Initial value

Reserved

: Type

: Initial value

Reserved

RSTFIFO

EXFER

Reserved

R/W

: Type

0x0

: Initial value

Reserved

REQDLY

ERRIE NCCMPIE NTCMPIE CHNEN XFRACT Reserved BSWAP

XFRSIZE

XFRDIRC

CHRST

R/W

R/W : Type

0x0

0x1

: Initial value

Bit

Mnemonic

Field Name

Description

Read/Write

63:22

Reserved

⎯

RSTFIFO

Reset FIFO

Reset FIFO (Default: 0x0)

Initializes the Read pointer and Write pointer to the FIFO in the PDMAC,

and sets the FIFO hold count to “0”. Please use the software to clear this

bit when it is set.

This is a function for a diagnosis. Usually, it is not used.

1: Performs FIFO reset.

0: Does not perform FIFO reset.

R/W

EXFER

Endian Transfer

Endian Transfer (Default: 0x0)

Specifies whether to perform Endian transfer. Please use the default as is.

Set up EXFER as follows according to a Endian setup of G-Bus.

1: G-Bus in Little Endian

0: G-Bus in Big Endian

R/W

19:14

Reserved

⎯

13:11

REQDLY

Request Delay

Time

Request Delay (Default: 0x0)

G-Bus transactions for DMA transfer must be performed separated at least

by the interval this field specifies.

000: Continuously try to perform G-Bus transfer.

001: 16 G-Bus clocks

010: 32 G-Bus clocks

011: 64 G-Bus clocks

100: 128 G-Bus clocks

101: 256 G-Bus clocks

110: 512 G-Bus clocks

111: 1024 G-Bus clocks

R/W

ERRIE

Error Detect

Interrupt Enable

Interrupt Enable on Error (Default: 0x0)

1: PDMAC generates an error during error detection.

0: PDMAC does not generate an error during error detection.

R/W

NCCMPIE

Normal Chain

Complete

Interrupt Enable

Interrupt Enable on Chain Done (Default: 0x0)

1: PDMAC generates an interrupt when the current chain is complete.

0: PDMAC does not generate an interrupt when the current chain is

complete.

R/W

Figure 10.4.60 PDMAC Configuration Register (1/2)

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