TMPR4937 datasheet(334/552 Pages) TOSHIBA

334 / 552 page

Chapter 10 PCI Controller

10-76

10.4.45 PCI Controller Interrupt Mask Register (PCICMASK)

0xD178

Reserved

: Type

: Initial value

Reserved

PMEIE TLBIE NIBIE ZIBIE Reserved PERRIE SERRIE GBEIE

Reserved

R/W

: Type

0x0

: Initial value

Bit

Mnemonic

Field Name

Description

Read/Write

31:11

Reserved

⎯

PMEIE

PME Detect

Interrupt Enable

PME* Signal Interrupt Enable (Default: 0x0)

When in the Host mode, this bit generates an interrupt when input of the

PME* signal is detected.

1: Generates an interrupt.

0: Does not generate an interrupt.

R/W

TLBIE

Long Burst

Transfer Detect

Interrupt

Too Long Burst Interrupt Enable (Default: 0x0)

This bit generates an interrupt when a Burst transfer by the on-chip DMA

Controller exceeding 8 DWORDs was detected.

1: Generates an interrupt.

0: Does not generate an interrupt

R/W

NIBIE

Negative

Increment Burst

Transfer Detect

Interrupt Enable

Negative Increment Burst Interrupt Enable (Default: 0x0)

This bit generates an interrupt when a negative direction Burst transfer by

the on-chip DMA Controller is detected.

1: Generates an interrupt.

0: Does not generate an interrupt.

R/W

ZIBIE

Zero Increment

Burst Transfer

Detect Interrupt

Enable

Zero Increment Burst Interrupt Enable (Default: 0x0)

This bit generates an interrupt when a Burst transfer by the on-chip DMA

Controller without an address increment is detected.

1: Generates an interrupt.

0: Does not generate an interrupt.

R/W

Reserved

⎯

PERRIE

PERR* Detect

Interrupt Enable

PERR* Interrupt Enable (Default: 0x0)

This bit generates an interrupt when the Parity Error signal (PERR*) is

asserted.

1: Generates an interrupt.

0: Does not generate an interrupt.

R/W

SERRIE

SERR* Detect

Interrupt Enable

SERR* Interrupt Enable (Default: 0x0)

This bit generates an interrupt when the System Error signal (SERR*) is

asserted.

1: Generates an interrupt.

0: Does not generate an interrupt.

R/W

GBEIE

G-Bus Bus Error

Detect Interrupt

Enable

G-Bus Bus Error Interrupt Enable (Default: 0x0)

This bit generates an interrupt when a Bus Error is asserted while the PCI

Controller is the G-Bus Master.

1: Generates an interrupt.

0: Does not generate an interrupt.

R/W

2:0

Reserved

⎯

Figure 10.4.43 PCI Controller Interrupt Mask Register

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