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TMPR4937 bảng dữ liệu(PDF) 337 Page - Toshiba Semiconductor |
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TMPR4937 bảng dữ liệu(HTML) 337 Page - Toshiba Semiconductor |
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337 / 552 page ![]() Chapter 10 PCI Controller 10-79 10.4.48 P2G Memory Space 2 G-Bus Base Address Register (P2GM2GBASE) 0xD190 63 48 Reserved : Type : Initial value 47 39 38 37 36 35 32 Reserved P2GM2EN BSWAP EXFER BA[35:32] R/W R/W R/W R/W : Type 0x0 0x0/0x1 0x1/0x0 0x0 : Initial value 31 20 19 16 BA[31:20] Reserved R/W : Type 0x000 : Initial value 15 0 Reserved : Type : Initial value Bit Mnemonic Field Name Description Read/Write 63:39 Reserved ⎯ 38 P2GM2EN Memory Space 2 Enable Target Memory Space 2 Enable (Default: 0x0) Controls whether Memory Space 2 for target access is valid or invalid. When this bit is set to invalid, Writes to the Memory Space 2 Lower Base Address Register or the Memory Space 2 Upper Base Address Register of the PCI Configuration Register become invalid. Also, “0” is returned to Reads as a response. 1: Validates Memory Space 2 for target access. 0: Invalidates Memory Space 2 for target access. R/W 37 BSWAP Byte Swap Byte Swap Disable (Default: Little Endian Mode: 0x1; Big Endian Mode: 0x0) Sets the byte swapping of Memory Space 2 for target access. 1: Do not perform byte swapping. 0: Perform byte swapping. Please use the default state in most situations. If this bit is changed to “1” when in the Big Endian Mode, the byte order of transfer to Memory Space 2 through DWORD (32-bit) access will not change. R/W 36 EXFER Endian Transfer Endian Transfer (Default: Little Endian Mode: 0x0; Big Endian Mode: 0x1) Sets the Endian Transfer of Memory Space 2 for target access. 1: Performs Endian Transfer. 0: Does not perform Endian Transfer. Please use the default state. R/W 35:20 BA[35:20] Memory Space Base Address 2 Base Address 2 (Default: 0x000) Sets the G-Bus base bus address of Memory Space 2 for target access. Can set the base address in 1-MB units. R/W 19:0 Reserved ⎯ Figure 10.4.46 P2G Memory Space 2 G-Bus Base Address Register |
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