TMPR4937 datasheet(332/552 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-74

10.4.44 PCI Controller Status Register (PCICSTATUS)

0xD174

Reserved

: Type

: Initial value

Reserved

PME

TLB

NIB

ZIB

Reserved

PERR SERR GBE Reserved IWB E2PDONE

R/W1C R/W1C R/W1C R/W1C

R/W1C R/W1C R/W1C

: Type

0x0

⎯

: Initial value

Bit

Mnemonic

Field Name

Description

Read/Write

31:11

Reserved

⎯

PME

PME Detect

PME Detect (Default: 0x0)

When the PCI Controller is in the Host mode, this bit indicates that

assertion of the PME* signal was detected.

1: Indicates that assertion of the PME* signal was detected.

0: Indicates that assertion of the PME* signal was not detected.

R/W1C

TLB

Long Burst

Transfer Detect

Too Long Burst Detect (Default: 0x0)

Indicates that a Burst transfer by the on-chip DMA Controller exceeding 8

DWORDs was detected.

1: Indicates that a Burst transfer exceeding 8 DWORDs was detected.

0: Indicates that no Burst transfer exceeding 8 DWORDs was detected.

R/W1C

NIB

Negative

Increment Burst

Detect

Negative Increment Burst Detect (Default: 0x0)

Indicates that Burst transfer by the on-chip DMA Controller in the negative

direction was detected.

1: Indicates that a Burst transfer in the negative direction was detected.

0: Indicates that no Burst transfer in the negative direction was detected.

R/W1C

ZIB

Zero Increment

Burst Detect

Zero Increment Burst Detect (Default: 0x0)

Indicates that Burst transfer by the on-chip DMA Controller without an

address increment was detected.

1: Indicates that a Burst transfer without an address increment was

detected.

0: Indicates that no Burst transfer without an address increment was

detected.

R/W1C

Reserved

⎯

PERR

PERR* Detected

PERR* Occurred (Default: 0x0)

Indicates that the Parity Error signal (PERR*) was asserted. This bit is a

monitor status bit that records assertion of the PERR* signal even if the

TX4937 is not accessing PCI.

1: Indicates that the PERR* signal was asserted.

0: Indicates that the PERR* signal was not asserted.

R/W1C

SERR

SERR* Detected

SERR* Occurred (Default: 0x0)

Indicates that the System Error signal (SERR*) was asserted. This bit is a

monitor status bit that records assertion of the SERR* signal even if the

TX4937 is not accessing PCI.

1: Indicates that the SERR* signal was asserted.

0: Indicates that the SERR* signal was not asserted.

R/W1C

GBE

G-Bus Error

Detect

G-Bus Error Detect (Default: 0x0)

Indicates that a G-Bus Error occurred in the G-Bus Master cycle of the PCI

Controller. This error is indicated when a timeout occurs on the G-Bus. This

bit is only set by Master cycle Bus Errors.

1: Indicates that a G-Bus Error was detected.

0: Indicates that no G-Bus Error was detected.

R/W1C

Figure 10.4.42 PCI Controller Status Register (1/2)

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