RT3612EB datasheet(28/47 Pages) RICHTEK

28 / 47 page

RT3612EB

DS3612EB-02 December 2019

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Dynamic VID (DVID) Compensation

During DVID transition, an extra current is required to

charge output capacitance for increasing voltage. The

charging current approximates to the product of the DVID

slew rate and output capacitance. For droop system, the

extra charging current induces extra voltage droop so that

the output voltage cannot reach target within the specified

time. The extra voltage drop approximates to DVID Slew

Rate x Output Capacitance x RLL (RLLis the loadline slope,

Ω). This phenomenon is called droop effect. How charging

current affects loop is illustrated in Figure 11. The

RT3612EB provides one DVID compensation function as

shown in Figure 12. An internal current IDVID_LIFT is sinking

internally from FB pin to generate DVID compensation

IDVID_LIFT x REA1. IDVID_LIFT for 50mV/

μs DVID SR can be

set from TSEN PIN-SETTING of DVID_LIFT, disabled or

5uA. For different scale of DVID SR, IDVID_LIFT is internally

Figure 11. Droop Effect in VID Transition

VSEN

Droop Effect

Charging

Current

for DVID

Inductor Current

VID

Figure 12. DVID Compensation

adjusted. Compensating magnitude can also be adjusted

by REA1. For IMVP9 specification, output voltage should

be within target TOB at 3us after Alert# assertion. While

DAC just arrives target (Alert issue timing), inductor current

is still high and needs a time to settle down to the DC

loading current. In the settling time, the falling down current

keeps to charge output capacitance (The magnitude is

related with inductor, capacitance and VID). Thus DVID

compensation can be less than DVID Slew Rate x Output

Capacitance (Capacitance degeneration should be

considered). While output capacitance is so large that

DVID compensation cannot cover, adding resistor and

capacitance from FB to GND also can provide similar

function. ERROR AMP compensation (resistance and

capacitance network among VSEN, FB and COMP) also

affects DVID behavior. The final setting should be based

on actual measurement.

VIN

Gate

Driver

RESR

CO2

CO1

Current

Sense

VID

IDVID_LIFT

REA1

REA2

TON

GEN/

Driver

Interface

PWM

CMP

DCR

Charging

Current

for DVID

Inductor Current

VID

DVID Compensation

Improved VSEN

Optional for extra large

ouput capacitance

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