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RT3612EB bảng dữ liệu(PDF) 44 Page - Richtek Technology Corporation |
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RT3612EB bảng dữ liệu(HTML) 44 Page - Richtek Technology Corporation |
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44 / 47 page ![]() RT3612EB 44 DS3612EB-02 December 2019 www.richtek.com © Copyright 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Under Voltage Protection When the output voltage is lower than VID-660mV with 3us filter time, UVP is triggered and PWMx are in tri- state to turn off high-side and low-side power MOSFETs. UVP is masked during DVID period and 80 μs after VID settles. The mechanism is illustrated in Figure 31. Figure 31. Under Voltage Mechanism All protections are reset only by VCC/EN toggle. UVP and OCP protections are listed in Table 19. Figure 30. Over Voltage Protection Mechanism 0V OVP Threshold 350mV +- 50mV VSEN VR_READY VID Down (Slow Slew rate) Indicator 60µs PWM Table 19. Summary of UVP and OCP Protection Protection Type Protection Threshold Protection Action DVID Mask Time Protection Reset Sum OC for PS0 _, , 1 SUM OC PS0 CSx SOCP ICCMAX IMON EQ I R KVIMON DCR R PWM tri-state, VR_READY latched low DVID+80us VCC/EN Toggle Sum OC for non PS0 _, , 1 SUM OC PS1 CSx SOCP ICCMAX IMON EQ I R 0.5 K VIMON DCR R UV VID - 660mV VID 660mV VSEN UVP Threshold PWM VR_READY |
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