RT3612EB datasheet(15/47 Pages) RICHTEK

15 / 47 page

RT3612EB

DS3612EB-02 December 2019

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Application Information

Power-ON Sequence

In order to confirm sufficient power supply for proper

operation, the VR triggers UVLO if VCC pin drops below

4.3V (max). UVLO protection shuts down controller and

forces high-side MOSFET and low-side MOSFET off. When

VCC > 4.45, the RT3612EB issues POR = high and waits

for VRON signal. After POR = high and VRON > 0.7V,

controller powers on (Chip Enable = H) and starts VR

internal settings, which include internal circuit offset

correction and function settings (PIN-SETTING). Users

Figure 2. Typical Timing of Controller Power-On

can set multi-functions through SETx and TSEN pins.

Figure 2 shows the typical timing of controller power-on.

After all internal settings are done and VBOOT = 0V,

VR_READY asserts to inform system that controller is

ready to communicate with CPU. If VBOOT = 1.8V,

VR_READY asserts until DVID to VBOOT. VR_READY

asserts within 2.5ms (max) after Chip Enable = H (VRON

= H and VCC > 4.45V). The pull-high power of VRON pin

is recommended as 1.05V, the same power as SVID

interface. That can ensure SVID power is ready while

VRON = H. For the VR normal operation, VIN should be

ready before VCC and VCC is strongly suggested to be

ready before driver power(PVCC) to prevent current flowing

back to VCC from PVCC through PWMx pin or DRVEN

pin. Moreover, VRON must be the last one to asserts after

both VCC and PVCC are ready (>UVLO).

VR Initial Setting Mode

Chip Enable

(VRON=H and VCC>4.45V)

VR_READY

SVID Command

VSEN

PIN-SETTING

Mode

Offset

Cancellation1

Mode

Offset

Cancellation2

Mode

PVCC

VCC

VRON

VIN

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