RT3612EB datasheet(6/47 Pages) RICHTEK

6 / 47 page

RT3612EB

DS3612EB-02 December 2019

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

UVLO

Detects the VCC voltage. As VCC overs threshold,

controller issues POR = high and waits VRON. After both

POR and VRON are ready, then controller is enabled.

Loop Control/Protection Logic

It controls power-on/off sequence, protections, power state

transition, and PWM sequence.

DAC

Generates a reference VID voltage according to the VID

code sent by Control Logic. According to setVID

command, Control Logic dynamically changes VID voltage

to the target with required slew rate.

ERROR AMP

Inverts and amplifies the difference between output voltage

and VID with externally set finite DC gain. The output signal

is COMP for PWM trigger.

PER CSGM

Senses per-phase inductor current. The outputs are used

for loop response, current balance, zero current detection,

current reporting and over-current protection.

SUM CSGM

Senses total inductor current with RIMON gain adjustment.

SUM CSGM output current ratio can also be set by PIN-

SETTING (Ai[1:0]). It helps wider application range of DCR

and load line. SUM CSGM output is used for PWM trigger.

RAMP

RAMP helps loop stability and transient response.

PWM CMP

The PWM comparator compares COMP signal and sum

current signal based on RAMP to trigger PWM.

Offset Cancellation

Cancel the current signal/comp voltage ripple issue to

control output voltage accuracy.

Current Balance

Per-phase current sense signal is compared with sensed

average current. The comparison result adjusts each phase

PWM width to optimize current and thermal balance.

Zero Current Detection

Detects whether each phase current crosses zero current.

The result is used for DEM power saving and overshoot

reduction (Anti-overshoot function).

AQR/ANTIOVS

AQR is a new generation of quick response mechanism

(Adaptive Quick Response, AQR) which detects loading

rising edge and allows all PWM to turn on. PWM pulse

width triggered by AQR is adaptive to loading level. AQR

trigger level can be set by PIN-SETTING. ANTIOVS can

help overshoot reduction which detects loading falling edge

and forces all PWM in tri-state until the zero current is

detected.

TONGEN/Driver Interface

PWM comparator output signal triggers TONGEN to

generate PWM pulse. The PWM sequence is controlled

by loop control. PWM pulse width is determined by

frequency setting, current balance output and adaptive

quick response (AQR) settings. Once AQR is triggered,

VR allows all PWM to turn on at the same time. Driver

Interface provides high/low/tri-state to drive external driver.

In power saving mode, driver interface force PWM in tri-

state to turn off high side and low side power MOSFET

according to zero current detection output. In addition,

PWM state is controlled by protection logic. Different

protections force required PWM state.

OVP/UVP/OCP

Over-voltage protection/Under-voltage protection/Over-

current protection.

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