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RT3612EB bảng dữ liệu(PDF) 32 Page - Richtek Technology Corporation |
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RT3612EB bảng dữ liệu(HTML) 32 Page - Richtek Technology Corporation |
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32 / 47 page ![]() RT3612EB 32 DS3612EB-02 December 2019 www.richtek.com © Copyright 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Dual Ramp Mechanism Normal controllers easily suffer jitter and stability issues under low equivalent series resistance (ESR) of capacitor application and large loop delay condition. The large Loop delay often comes from PCB parasitic inductance. Figure 17 illustrates how PCB parasitic inductance impact the load transient response. The PCB parasitic inductance delays energy delivering and causes VSEN to keep falling. The dropping VSEN induces several successive PWM pulses and then VSEN ring-back occurs. While load current release at the ring back region, it will generate large overshoot. Thus more capacitors will use for the overshoot reduction. Figure 17. Load Transient Response with PCB Parasitic Inductance Loading Current ΔIcc VSEN PH1 PH2 |
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