PM7344 datasheet(175/293 Pages) PMC

175 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

159

11.1

Registers x49-x4FH: Latching Performance Data

All the Performance Data registers for one of the four interfaces on the S/UNI-

MPH are updated as a group by writing to any of the PMON count registers

(addresses x49H-x4FH). A write to any of these locations loads performance

data located in the PMON block into the internal holding registers. The data

contained in the holding registers can then be subsequently read by

microprocessor accesses into the PMON block count register address space.

The latching of count data, and subsequent resetting of the counters, is

synchronized to the internal event timing so that no events are missed. NOTE: it

is necessary to write to one, and only one, count register address to latch all the

count data register values into the holding registers and to reset all the counters

for each polling cycle.

Alternately, one may write to the Global Monitoring Update register (00CH) to

transfer the contents of each of the four PMON blocks, along with ATM cell

monitoring information from each of the four RXCP and TXCP blocks at the

same time. The transfer in progress (TIP) bit in register 00CH is polled to

determine when the transfer is complete.

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