PM7344 datasheet(156/293 Pages) PMC

156 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

140

Registers 03BH, 13BH, 23BH and 33BH: RFDL Receive Data

Bit

Type

Function

Default

Bit 7

RD7

Bit 6

RD6

Bit 5

RD5

Bit 4

RD4

Bit 3

RD3

Bit 2

RD2

Bit 1

RD1

Bit 0

RD0

RD0 corresponds to the first bit of the serial byte received by the RFDL.

These registers are actually 4 level FIFOs. If data is available, the FE bit in the

Status register is low. If INTC[1:0] (in the Enable/Status register) is set to 01, the

Receive Data register must be read within 31 data bit periods to prevent an

overrun. If INTC[1:0] is set to 11 the Receiver Data register must be read within

15 data bit periods.

When an overrun is detected, an interrupt is generated and the FIFO is held

cleared until the Status register is read. When the HDLC abort sequence

(01111111) is detected in the data an ABORT interrupt is generated and the data

that has been shifted into the serial to parallel converter is written into the FIFO.

A read of the Receive Data register increments the FIFO pointer at the end of the

read. If the Receive Data register read causes a FIFO underrun, then the pointer

is inhibited from incrementing. The underrun condition will be signaled in the

next Status read by returning all zeros.

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