LPC55S2X datasheet(92/132 Pages) NXP

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NXP Semiconductors

LPC55S2x/LPC552x

32-bit Arm Cortex®-M33 microcontroller

SCK (CPOL = 0)

MISO (CPHA = 1)

SSEL

MOSI (CPHA = 1)

Tcy(clk)

tDS

tDH

tv(Q)

DATA VALID (LSB)

DATA VALID

tv(Q)

SCK (CPOL = 1)

DATA VALID (LSB)

DATA VALID

MISO (CPHA = 0)

MOSI (CPHA = 0)

tDS

tDH

DATA VALID (MSB)

DATA VALID

DATA VALID (LSB)

tv(Q)

DATA VALID (MSB)

DATA VALID

tv(Q)

DATA VALID (MSB)

IDLE

DATA VALID (MSB)

Figure 21. SPI slave timing

11.13 USART interface

The actual USART bit rate depends on the delays introduced by the external trace, the external device, system

clock (CCLK), and capacitive loading. Excluding delays introduced by external device and PCB, the maximum

supported bit rate for USART master and slave synchronous mode is 25 Mbit/s. Excluding delays introduced by

external device and PCB, the maximum supported bit rate for USART master and slave asynchronous mode is

10 Mbit/s.

Tamb = -40 °C to 105 °C; VDD = 1.8 V to 3.6 V; CL = 10 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =

fast-mode for all pins; Parameters sampled at the 50% level of the rising or falling edge.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

USART master (in synchronous mode)

tsu(D)

data input set-up time

th(D)

data input hold time

tv(Q)

data output valid time

USART slave (in synchronous mode)

tsu(D)

data input set-up time

th(D)

data input hold time

Table 37. USART dynamic characteristics[1]

LPC55S2X_LPC552X

All information provided in this document is subject to legal disclaimers.

Data sheet

Rev. 2.3 — 29 August 2024

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