LPC55S2X datasheet(63/132 Pages) NXP

63 / 132 page

NXP Semiconductors

LPC55S2x/LPC552x

32-bit Arm Cortex®-M33 microcontroller

– Sixteen events.

– Thirty two states.

– Upon match and/or an input or output transition create the following events: interrupt; stop, limit, halt the

timer or change counting direction; toggle outputs; change the state.

– Counter value can be loaded into capture register triggered by a match or input/output toggle.

• PWM features:

– Counters can be used in conjunction with match registers to toggle outputs and create time-proportioned

PWM signals.

– Up to ten single-edge or eight dual-edge PWM outputs with independent duty cycle and common PWM

cycle length.

• Event creation features:

– The following conditions define an event: a counter match condition, an input (or output) condition such as

an rising or falling edge or level, a combination of match and/or input/output condition.

– Selected events can limit, halt, start, or stop a counter or change its direction.

– Events trigger state changes, output toggles, interrupts, and DMA transactions.

– Match register 0 can be used as an automatic limit.

– In bi-directional mode, events can be enabled based on the count direction.

– Match events can be held until another qualifying event occurs.

• State control features:

– A state is defined by events that can happen in the state while the counter is running.

– A state changes into another state as a result of an event.

– Each event can be assigned to one or more states.

– State variable allows sequencing across multiple counter cycles.

7.25.3 Windowed WatchDog Timer (WWDT)

The purpose of the Watchdog Timer is to reset or interrupt the microcontroller within a programmable time if

it enters an erroneous state. When enabled, a watchdog reset is generated if the user program fails to feed

(reload) the Watchdog within a predetermined amount of time.

7.25.3.1 Features

• Internally resets chip if not reloaded during the programmable time-out period.

• Optional windowed operation requires reload to occur between a minimum and maximum time period, both

programmable.

• Optional warning interrupt can be generated at a programmable time prior to watchdog time-out.

• Programmable 24-bit timer with internal fixed pre-scaler.

• Selectable time period from 1,024 watchdog clocks (TWDCLK × 256 × 4) to over 67 million watchdog clocks

(TWDCLK × 224 × 4) in increments of four watchdog clocks.

• "Safe" watchdog operation. Once enabled, requires a hardware reset or a Watchdog reset to be disabled.

• Incorrect feed sequence causes immediate watchdog event if enabled.

• The watchdog reload value can optionally be protected such that it can only be changed after the "warning

interrupt" time is reached.

• Flag to indicate Watchdog reset.

• The watchdog clock (WDCLK) is generated from always on FRO_1MHz clock which can be divided by WDT

clock divider register. The accuracy of this clock is limited to +/- 15% over temperature, voltage, and silicon

processing variations.

• The Watchdog timer can be configured to run in Deep-sleep mode.

• Debug mode.

LPC55S2X_LPC552X

All information provided in this document is subject to legal disclaimers.

Data sheet

Rev. 2.3 — 29 August 2024

Document feedback

63 / 132

LPC55S2X bảng dữ liệu(PDF) 63 Page - NXP Semiconductors

LPC55S2X bảng dữ liệu(HTML) 63 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL