LPC55S2X datasheet(68/132 Pages) NXP

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NXP Semiconductors

LPC55S2x/LPC552x

32-bit Arm Cortex®-M33 microcontroller

7.28.1 AES engine

The LPC55S2x devices provide an on-chip hardware AES encryption and decryption engine to protect the

image content and to accelerate processing for data encryption or decryption, data integrity, and proof of origin.

Data can be encrypted or decrypted by the AES engine using a key from the PUF or a software supplied key.

The AES engine supports 128 bit, 192 bit, or 256 bit keys for encryption and decryption operations.

7.28.1.1 Features

• Encryption and decryption of data.

• Secure storage of AES key that cannot be read.

• Supports 128 bit, 192 bit or 256 bit key in Electronic Code Book (ECB) mode, Cipher Block Chaining (CBC)

mode, and Counter (CTR) mode.

• Supports 128-bit key in ICB (Indexed Code Book) mode, that offers protection against side-channel attacks.

• Compliant with the FIPS (Federal Information Processing Standard) Publication 197, Advanced Encryption

Standard (AES).

• It may use the processor, DMA, or AHB Master for data movement. AHB Master may only be used to load

data, DMA may be used to read-out results. DMA based result reading is a "trigger", so the application must

set the size correctly.

7.28.2 HASH engine

The LPC55S2x devices provide on-chip Hash support to perform SHA-1 and SHA-2 with 256-bit digest

(SHA-256). Hashing is a way to reduce arbitrarily large messages or code images to a relatively small fixed

size "unique" number called a digest. The SHA-1 Hash produces a 160 bit digest (five words), and the SHA-256

hash produces a 256 bit digest (eight words).

7.28.2.1 Features

• Performs SHA-1 and SHA-2(256) based hashing.

• Used with HMAC to support a challenge/response or to validate a message.

7.28.3 PUF

The PUF controller on the LPC55S2x provides generation and secure storage for keys without storing the

key. The PUF controller provides a unique key per device and exists in that device based on the unique

characteristics of PUF SRAM. Instead of storing the key, a Key Code is generated, which in combination with

the digital fingerprint is used to reconstruct keys that are routed to the AES engine, for use by software, and by

PRINCE engine. PUF keys have a dedicated path to the AES engine and PRINCE engine. There is no other

mechanism by which keys can be observed.

7.28.3.1 Features

• Key strength of 256-bits.

• The PUF constructs 256-bit strength device unique PUF root key using the digital fingerprint of a device

derived from SRAM and error correction data called Activation Code (AC). The Activation Code (AC) is

generated during enrollment process. The Activation Code (AC) should be stored on external non-volatile

memory device in the system.

• Generation, storage, and reconstruction of keys.

• Key sizes from 64 bits to 4096 bits.

• PUF controller allows storage of keys, generated externally or on chip, of sizes 64 bits to 4096 bits.

LPC55S2X_LPC552X

All information provided in this document is subject to legal disclaimers.

Data sheet

Rev. 2.3 — 29 August 2024

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