LPC55S2X datasheet(87/132 Pages) NXP

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NXP Semiconductors

LPC55S2x/LPC552x

32-bit Arm Cortex®-M33 microcontroller

Tamb = -40 °C to 105 °C; VBAT_DCDC = 1.8 V to 3.6 V; CL = 10 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW

setting = standard mode for all pins; Parameters sampled at the 50% level of the rising or falling edge.

Symbol

Parameter

Conditions

Min

Typ[3]

Max

Unit

45%

55%

Tcyc

tWL

pulse width LOW

on pins I2Sx_TX_SCK and I2Sx_RX_SCK[4]

45%

55%

Tcyc

Master; 1.8 V ≤ VDD < 3.6 V

tv(Q)

data output valid time

on pin I2Sx_TX_SDA

[5]

on pin I2Sx_WS

tsu(D)

data input set-up time

on pin I2Sx_RX_SDA

[5]

th(D)

data input hold time

on pin I2Sx_RX_SDA

[5]

Slave; 1.8 V ≤ VDD < 3.6 V

tv(Q)

data output valid time

on pin I2Sx_TX_SDA

[5]

on pin I2Sx_RX_SDA

[5]

on pin I2Sx_WS

tsu(D)

data input set-up time

on pin I2Sx_RX_SDA

[5]

on pin I2Sx_WS

th(D)

data input hold time

Table 34. Dynamic characteristics: I2S-bus interface pins[1][2]...continued

[1]

Based on simulation; not tested in production.

[2]

The Flexcomm Interface function clock frequency should not be above 48 MHz. See the data rates section in the I2S chapter (UM11126) to calculate clock

and sample rates.

[3]

Typical ratings are not guaranteed.

[4]

Based on simulation. Not tested in production.

[5]

Clock Divider register (DIV) = 0x0.

LPC55S2X_LPC552X

All information provided in this document is subject to legal disclaimers.

Data sheet

Rev. 2.3 — 29 August 2024

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