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PIC18F44J10-E/ML bảng dữ liệu(PDF) 187 Page - Microchip Technology |
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PIC18F44J10-E/ML bảng dữ liệu(HTML) 187 Page - Microchip Technology |
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187 / 358 page  © 2007 Microchip Technology Inc. Preliminary DS39682C-page 185 PIC18F45J10 FAMILY TABLE 15-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 43 PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 45 PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 45 IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 45 PIR2 OSCFIF CMIF — — BCL1IF — — CCP2IF 45 PIE2 OSCFIE CMIE — — BCL1IE — — CCP2IE 45 IPR2 OSCFIP CMIP — — BCL1IP — — CCP2IP 45 PIR3 SSP2IF BCL2IF — — — — — —45 PIE3 SSP2IE BCL2IE — — — — — —45 IPR3 SSP2IP BCL2IP — — — — — —45 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 46 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 46 SSP1BUF MSSP1 Receive Buffer/Transmit Register 44 SSP1ADD MSSP1 Address Register (I2C™ Slave mode). MSSP1 Baud Rate Reload Register (I2C Master mode). 44 SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 44 SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 44 SSP1STAT SMP CKE D/A PS R/W UA BF 44 SSP2BUF MSSP2 Receive Buffer/Transmit Register 46 SSP2ADD MSSP2 Address Register (I2C Slave mode). MSSP2 Baud Rate Reload Register (I2C Master mode). 46 SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 46 SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 46 SSP2STAT SMP CKE D/A PS R/W UA BF 46 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode. Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’. |
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