PIC18F44J10-ESLASHML datasheet(75/358 Pages) MICROCHIP

75 / 358 page

Preliminary

DS39682C-page 73

PIC18F45J10 FAMILY

6.5

Writing to Flash Program Memory

The minimum programming block is 32 words or

64 bytes. Word or byte programming is not supported.

Table writes are used internally to load the holding

registers needed to program the Flash memory. There

are 64 holding registers used by the table writes for

programming.

Since the Table Latch (TABLAT) is only a single byte, the

TBLWT

instruction may need to be executed 64 times for

each programming operation. All of the table write

operations will essentially be short writes because only

the holding registers are written. At the end of updating

the 64 holding registers, the EECON1 register must be

written to in order to start the programming operation

with a long write.

The long write is necessary for programming the inter-

nal Flash. Instruction execution is halted while in a long

write cycle. The long write will be terminated by the

internal programming timer.

The EEPROM on-chip timer controls the write time.

The write/erase voltages are generated by an on-chip

charge pump, rated to operate over the voltage range

of the device.

FIGURE 6-5:

TABLE WRITES TO FLASH PROGRAM MEMORY

6.5.1

FLASH PROGRAM MEMORY WRITE

SEQUENCE

The sequence of events for programming an internal

program memory location should be:

If the section of program memory to be written to

has been programmed previously, then the

memory will need to be erased before the write

occurs (see 6.4.1 “Flash Program Memory

Erase Sequence”).

Write the 64 bytes into the holding registers with

auto-increment.

Set the EECON1 register for the write operation:

• set WREN to enable byte writes.

Disable interrupts.

Write 55h to EECON2.

Write 0AAh to EECON2.

Set the WR bit. This will begin the write cycle.

The CPU will stall for duration of the write (about

2 ms using internal timer).

Re-enable interrupts.

10. Verify the memory (table read).

An example of the required code is shown in

Example 6-3.

Note:

Unlike previous devices, the PIC18F45J10

family of devices does not reset the holding

registers after a write occurs. The holding

registers must be cleared or overwritten

before a programming sequence.

In order to maintain the endurance of the

cells, each Flash byte should not be

programmed more then twice between

erase operations. Either a bulk or row

erase of the target row is required before

attempting to modify the contents a third

time.

TABLAT

TBLPTR = xxxx3F

TBLPTR = xxxxx1

TBLPTR = xxxxx0

Write Register

TBLPTR = xxxxx2

Program Memory

Holding Register

Note:

Before setting the WR bit, the Table

Pointer address needs to be within the

intended address range of the 64 bytes in

the holding register.

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