PIC18F44J10-ESLASHML datasheet(28/358 Pages) MICROCHIP

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PIC18F45J10 FAMILY

DS39682C-page 26

Preliminary

2.5

Internal Oscillator Block

The PIC18F45J10 family of devices includes an inter-

nal oscillator source (INTRC) which provides a nominal

31 kHz output. The INTRC is enabled on device

power-up and clocks the device during its configuration

cycle until it enters operating mode. INTRC is also

enabled if it is selected as the device clock source or if

any of the following are enabled:

• Fail-Safe Clock Monitor

• Watchdog Timer

• Two-Speed Start-up

These features are discussed in greater detail in

Section 20.0 “Special Features of the CPU”.

The INTRC can also be optionally configured as the

default clock source on device start-up by setting the

FOSC2

configuration

bit.

This

discussed

Section 2.6.1 “Oscillator Control Register”.

2.6

Clock Sources and

Oscillator Switching

The PIC18F45J10 family includes a feature that allows

the device clock source to be switched from the main

oscillator to an alternate clock source. PIC18F45J10

family devices offer two alternate clock sources. When

an alternate clock source is enabled, the various

power-managed operating modes are available.

Essentially, there are three clock sources for these

devices:

• Primary oscillators

• Secondary oscillators

• Internal oscillator

The primary oscillators include the External Crystal

and Resonator modes and the External Clock modes.

The particular mode is defined by the FOSC2:FOSC0

configuration bits. The details of these modes are

covered earlier in this chapter.

The secondary oscillators are those external sources

not connected to the OSC1 or OSC2 pins. These

sources may continue to operate even after the

controller is placed in a power-managed mode.

PIC18F45J10 family devices offer the Timer1 oscillator

as a secondary oscillator. This oscillator, in all

power-managed modes, is often the time base for

functions such as a real-time clock.

Most often, a 32.768 kHz watch crystal is connected

between the RC0/T1OSO/T13CKI and RC1/T1OSI

pins. Loading capacitors are also connected from each

pin to ground.

The Timer1 oscillator is discussed in greater detail in

Section 11.3 “Timer1 Oscillator”.

In addition to being a primary clock source, the internal

oscillator is available as a power-managed mode

clock source. The INTRC source is also used as the

clock source for several special features, such as the

WDT and Fail-Safe Clock Monitor.

The clock sources for the PIC18F45J10 family devices

are shown in Figure 2-5. See Section 20.0 “Special

Features of the CPU” for Configuration register

details.

FIGURE 2-5:

PIC18F45J10 FAMILY CLOCK DIAGRAM

PIC18F45J10 Family

4 x PLL

FOSC2:FOSC0

T1OSCEN

Enable

Oscillator

T1OSO

T1OSI

Clock Source Option

for other Modules

OSC1

OSC2

Sleep

HSPLL, ECPLL

HS, EC

T1OSC

CPU

Peripherals

IDLEN

INTRC

Source

WDT, PWRT, FSCM

Internal Oscillator

Clock

Control

OSCCON<1:0>

and Two-Speed Start-up

Primary Oscillator

Secondary Oscillator

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