PIC18F44J10-ESLASHML datasheet(41/358 Pages) MICROCHIP

41 / 358 page

Preliminary

DS39682C-page 39

PIC18F45J10 FAMILY

4.2

Master Clear (MCLR)

The MCLR pin provides a method for triggering a hard

external Reset of the device. A Reset is generated by

holding the pin low. PIC18 extended microcontroller

devices have a noise filter in the MCLR Reset path

which detects and ignores small pulses.

The MCLR pin is not driven low by any internal Resets,

including the WDT.

4.3

Power-on Reset (POR)

A Power-on Reset condition is generated on-chip

whenever VDD rises above a certain threshold. This

allows the device to start in the initialized state when

VDD is adequate for operation.

To take advantage of the POR circuitry, tie the MCLR

pin through a resistor (1 k

Ω to 10 kΩ) to VDD. This will

eliminate external RC components usually needed to

create a Power-on Reset delay. A minimum rise rate for

VDD is specified (parameter D004). For a slow rise

time, see Figure 4-2.

When the device starts normal operation (i.e., exits the

Reset

condition),

device

operating

parameters

(voltage, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

conditions are met.

POR events are captured by the POR bit (RCON<1>).

The state of the bit is set to ‘0’ whenever a POR occurs;

it does not change for any other Reset event. POR is

not reset to ‘1’ by any hardware event. To capture

multiple events, the user manually resets the bit to ‘1’

in software following any POR.

4.4

Brown-out Reset (BOR)

(PIC18F2X1X/4X1X Devices Only)

Once a BOR has occurred, the Power-up Timer will

keep the chip in Reset for TPWRT (parameter 33). If

VDD drops below VBOR while the Power-up Timer is

running, the chip will go back into a Brown-out Reset

and the Power-up Timer will be initialized. Once VDD

rises above VBOR, the Power-up Timer will execute the

additional time delay.

FIGURE 4-2:

EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

4.4.1

DETECTING BOR

The BOR bit always resets to ‘0’ on any BOR or POR

event. This makes it difficult to determine if a BOR

event has occurred just by reading the state of BOR

alone. A more reliable method is to simultaneously

check the state of both POR and BOR. This assumes

that the POR bit is reset to ‘1’ in software immediately

after any POR event. If BOR is ‘0’ while POR is ‘1’, it

can be reliably assumed that a BOR event has

occurred.

In devices designated with an “LF” part number (such

as PIC18LF25J10), Brown-out Reset functionality is

disabled. In this case, the BOR bit cannot be used to

determine a BOR event. The BOR bit is still cleared by

a POR event.

Note 1:

External Power-on Reset circuit is required

only if the VDD power-up slope is too slow.

The diode D helps discharge the capacitor

quickly when VDD powers down.

R < 40 k

Ω is recommended to make sure that

the voltage drop across R does not violate

the device’s electrical specification.

≥ 1 kΩ will limit any current flowing into

MCLR from external capacitor C, in the event

of MCLR pin breakdown, due to Electrostatic

Discharge (ESD) or Electrical Overstress

(EOS).

VDD

MCLR

PIC18F45J10

VDD

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