PIC18F44J10-ESLASHML datasheet(95/358 Pages) MICROCHIP

95 / 358 page

Preliminary

DS39682C-page 93

PIC18F45J10 FAMILY

9.0

I/O PORTS

Depending on the device selected and features

enabled, there are up to five ports available. Some pins

of the I/O ports are multiplexed with an alternate

function from the peripheral features on the device. In

general, when a peripheral is enabled, that pin may not

be used as a general purpose I/O pin.

Each port has three registers for its operation. These

registers are:

• TRIS register (data direction register)

• Port register (reads the levels on the pins of the

device)

• LAT register (output latch)

The Data Latch (LAT register) is useful for read-modify-

write operations on the value that the I/O pins are

driving.

A simplified model of a generic I/O port, without the

interfaces to other peripherals, is shown in Figure 9-1.

FIGURE 9-1:

GENERIC I/O PORT

OPERATION

9.1

I/O Port Pin Capabilities

When developing an application, the capabilities of the

port pins must be considered. Outputs on some pins

have higher output drive strength than others. Similarly,

some pins can tolerate higher than VDD input levels.

9.1.1

PIN OUTPUT DRIVE

The output pin drive strengths vary for groups of pins

intended to meet the needs for a variety of applications.

PORTB and PORTC are designed to drive higher

loads, such as LEDs. All other ports are designed for

small loads, typically indication only. Table 9-1 sum-

marizes the output capabilities. Refer to Section 23.0

“Electrical Characteristics” for more details.

TABLE 9-1:

OUTPUT DRIVE LEVELS

9.1.2

INPUT PINS AND VOLTAGE

CONSIDERATIONS

The voltage tolerance of pins used as device inputs is

dependent on the pin’s input function. Pins that are used

as digital only inputs are able to handle DC voltages up

to 5.5V; a level typical for digital logic circuits. In contrast,

pins that also have analog input functions of any kind

can only tolerate voltages up to VDD. Voltage excursions

beyond VDD on these pins should be avoided. Table 9-2

summarizes

the

input

capabilities.

Refer

Section 23.0 “Electrical Characteristics” for more

details.

TABLE 9-2:

INPUT VOLTAGE LEVELS

Data

Bus

WR LAT

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

Input

Buffer

I/O pin(1)

RD LAT

or Port

Note 1:

I/O pins have diode protection to VDD and VSS.

Port

Drive

Description

PORTA

Minimum Intended for indication.

PORTD

PORTE

PORTB

High

Suitable for direct LED drive

levels.

PORTC

Port or Pin

Tolerated

Input

Description

PORTA<5:0>

VDD

Only VDD input levels

tolerated.

PORTB<5:0>

PORTC<1:0>

PORTE<2:0>

PORTB<7:6>

5.5V

Tolerates input levels

above VDD, useful for

most standard logic.

PORTC<7:2>

PORTD<7:0>

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