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PIC18F44J10-E/ML bảng dữ liệu(PDF) 185 Page - Microchip Technology

tên linh kiện PIC18F44J10-E/ML
Giải thích chi tiết về linh kiện  28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology
PDF  358 Pages
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nhà sản xuất  MICROCHIP [Microchip Technology]
Trang chủ  http://www.microchip.com
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PIC18F44J10-E/ML bảng dữ liệu(HTML) 185 Page - Microchip Technology

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© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 183
PIC18F45J10 FAMILY
15.4.17.2
Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
a)
A low level is sampled on SDAx when SCLx
goes from low level to high level.
b)
SCLx goes low before SDAx is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
When the user deasserts SDAx and the pin is allowed
to float high, the BRG is loaded with SSPxADD<6:0>
and counts down to ‘0’. The SCLx pin is then
deasserted and when sampled high, the SDAx pin is
sampled.
If SDAx is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, see
Figure 15-29). If SDAx is sampled high, the BRG is
reloaded and begins counting. If SDAx goes from
high-to-low before the BRG times out, no bus collision
occurs because no two masters can assert SDAx at
exactly the same time.
If SCLx goes from high-to-low before the BRG times
out and SDAx has not already been asserted, a bus
collision occurs. In this case, another master is
attempting to transmit a data ‘1’ during the Repeated
Start condition (see Figure 15-30).
If, at the end of the BRG time-out, both SCLx and SDAx
are still high, the SDAx pin is driven low and the BRG
is reloaded and begins counting. At the end of the
count, regardless of the status of the SCLx pin, the
SCLx pin is driven low and the Repeated Start
condition is complete.
FIGURE 15-29:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
FIGURE 15-30:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SDAx
SCLx
RSEN
BCLxIF
S
SSPxIF
Sample SDAx when SCLx goes high.
If SDAx = 0, set BCLxIF and release SDAx and SCLx.
Cleared in software
‘0’
‘0’
SDAx
SCLx
BCLxIF
RSEN
S
SSPxIF
Interrupt cleared
in software
SCLx goes low before SDAx,
set BCLxIF. Release SDAx and SCLx.
TBRG
TBRG
‘0’



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