PIC18F44J10-ESLASHML datasheet(176/358 Pages) MICROCHIP

176 / 358 page

PIC18F45J10 FAMILY

DS39682C-page 174

Preliminary

15.4.8

I2C MASTER MODE START

CONDITION TIMING

To initiate a Start condition, the user sets the Start

Enable bit, SEN (SSPxCON2<0>). If the SDAx and

SCLx pins are sampled high, the Baud Rate Generator

is reloaded with the contents of SSPxADD<6:0> and

starts its count. If SCLx and SDAx are both sampled

high when the Baud Rate Generator times out (TBRG),

the SDAx pin is driven low. The action of the SDAx

being driven low while SCLx is high is the Start condi-

tion and causes the S bit (SSPxSTAT<3>) to be set.

Following this, the Baud Rate Generator is reloaded

with the contents of SSPxADD<6:0> and resumes its

count. When the Baud Rate Generator times out

(TBRG), the SEN bit (SSPxCON2<0>) will be automati-

cally cleared by hardware. The Baud Rate Generator is

suspended, leaving the SDAx line held low and the

Start condition is complete.

15.4.8.1

WCOL Status Flag

If the user writes the SSPxBUF when a Start sequence

is in progress, the WCOL is set and the contents of the

buffer are unchanged (the write doesn’t occur).

FIGURE 15-19:

FIRST START BIT TIMING

Note:

If at the beginning of the Start condition,

the SDAx and SCLx pins are already sam-

pled low, or if during the Start condition, the

SCLx line is sampled low before the SDAx

line is driven low, a bus collision occurs.

The Bus Collision Interrupt Flag, BCLxIF,

is set, the Start condition is aborted and

the I2C module is reset into its Idle state.

Note:

Because queueing of events

not

allowed, writing to the lower 5 bits of

SSPxCON2 is disabled until the Start

condition is complete.

SDAx

SCLx

TBRG

1st bit

2nd bit

TBRG

SDAx = 1,

At completion of Start bit,

SCLx = 1

Write to SSPxBUF occurs here

TBRG

hardware clears SEN bit

TBRG

Write to SEN bit occurs here

Set S bit (SSPxSTAT<3>)

and sets SSPxIF bit

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