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PIC18F44J10-E/ML bảng dữ liệu(PDF) 175 Page - Microchip Technology |
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PIC18F44J10-E/ML bảng dữ liệu(HTML) 175 Page - Microchip Technology |
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175 / 358 page ![]() © 2007 Microchip Technology Inc. Preliminary DS39682C-page 173 PIC18F45J10 FAMILY 15.4.7.2 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCLx pin (SCLx allowed to float high). When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and begins counting. This ensures that the SCLx high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 15-18). FIGURE 15-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDAx SCLx SCLx deasserted but slave holds DX – 1 DX BRG SCLx is sampled high, reload takes place and BRG starts its count 03h 02h 01h 00h (hold off) 03h 02h Reload BRG Value SCLx low (clock arbitration) SCLx allowed to transition high BRG decrements on Q2 and Q4 cycles |
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