PIC18F44J10-ESLASHML datasheet(237/358 Pages) MICROCHIP

237 / 358 page

Preliminary

DS39682C-page 235

PIC18F45J10 FAMILY

20.2

Watchdog Timer (WDT)

For PIC18F45J10 family devices, the WDT is driven by

the INTRC oscillator. When the WDT is enabled, the

clock source is also enabled. The nominal WDT period

is 4 ms and has the same stability as the INTRC

oscillator.

The 4 ms period of the WDT is multiplied by a 16-bit

postscaler. Any output of the WDT postscaler is

selected by a multiplexor, controlled by the WDTPS bits

in Configuration Register 2H. Available periods range

from 4 ms to 131.072 seconds (2.18 minutes). The

WDT and postscaler are cleared whenever a SLEEP or

CLRWDT

instruction is executed, or a clock failure

(primary or Timer1 oscillator) has occurred.

20.2.1

CONTROL REGISTER

The WDTCON register (Register 20-9) is a readable

and writable register. The SWDTEN bit enables or

disables WDT operation.

FIGURE 20-1:

WDT BLOCK DIAGRAM

WDTCON: WATCHDOG TIMER CONTROL REGISTER

TABLE 20-2:

SUMMARY OF WATCHDOG TIMER REGISTERS

Note 1: The CLRWDT and SLEEP instructions

clear the WDT and postscaler counts

when executed.

2: When a CLRWDT instruction is executed,

the postscaler count will be cleared.

U-0

R/W-0

—

—SWDTEN(1)

bit 7

bit 0

bit 7-1

Unimplemented: Read as ‘0’

bit 0

SWDTEN: Software Controlled Watchdog Timer Enable bit(1)

= Watchdog Timer is on

= Watchdog Timer is off

Note 1: This bit has no effect if the configuration bit, WDTEN, is enabled.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset Values

on page

RCON

IPEN

—

POR

BOR

WDTCON

—

—SWDTEN

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.

INTRC Oscillator

WDT

Wake-up from

Reset

WDT

WDT Counter

Programmable Postscaler

1:1 to 1:32,768

Enable WDT

WDTPS3:WDTPD0

SWDTEN

CLRWDT

Power-Managed

Reset

All Device Resets

Sleep

INTRC Control

÷128

Modes

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