PIC18F44J10-ESLASHML datasheet(233/358 Pages) MICROCHIP

233 / 358 page

Preliminary

DS39682C-page 231

PIC18F45J10 FAMILY

CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)

CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)

R/WO-1

U-0

R/WO-1

DEBUG

XINST

STVREN

—

—WDTEN

bit 7

bit 0

bit 7

DEBUG: Background Debugger Enable bit

= Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins

= Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug

bit 6

XINST: Extended Instruction Set Enable bit

= Instruction set extension and Indexed Addressing mode enabled

= Instruction set extension and Indexed Addressing mode disabled (Legacy mode)

bit 5

STVREN: Stack Overflow/Underflow Reset Enable bit

= Reset on stack overflow/underflow enabled

= Reset on stack overflow/underflow disabled

bit 4-1

Unimplemented: Read as ‘0’

bit 0

WDTEN: Watchdog Timer Enable bit

= WDT enabled

= WDT disabled (control is placed on SWDTEN bit)

Legend:

R = Readable bit

WO = Write-once bit

U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed

‘1’ = Bit is set

‘0’ = Bit is cleared

U-0

R/WO-1

U-0

—

—(1)

CP0

—

bit 7

bit 0

bit 7-3

Unimplemented: Read as ‘0’

bit 2

CP0: Code Protection bit

= Program memory is not code-protected

= Program memory is code-protected

bit 1-0

Unimplemented: Read as ‘0’

Note 1: This bit should always be maintained as ‘0’.

Legend:

R = Readable bit

WO = Write-once bit

U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed

‘1’ = Bit is set

‘0’ = Bit is cleared

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