PIC18F44J10-ESLASHML datasheet(241/358 Pages) MICROCHIP

241 / 358 page

Preliminary

DS39682C-page 239

PIC18F45J10 FAMILY

FIGURE 20-5:

FSCM TIMING DIAGRAM

20.5.3

FSCM INTERRUPTS IN

POWER-MANAGED MODES

By entering a power-managed mode, the clock

multiplexor selects the clock source selected by the

OSCCON

Fail-Safe

Monitoring

the

power-managed

clock

source

resumes

the

power-managed mode.

If an oscillator failure occurs during power-managed

operation, the subsequent events depend on whether

or not the oscillator failure interrupt is enabled. If

enabled (OSCFIF = 1), code execution will be clocked

by the INTOSC multiplexor. An automatic transition

back to the failed clock source will not occur.

If the interrupt is disabled, subsequent interrupts while

in Idle mode will cause the CPU to begin executing

instructions while being clocked by the INTOSC

source.

20.5.4

POR OR WAKE-UP FROM SLEEP

The FSCM is designed to detect oscillator failure at any

point after the device has exited Power-on Reset

(POR) or low-power Sleep mode. When the primary

device clock is either EC or INTRC modes, monitoring

can begin immediately following these events.

For HS mode, the situation is somewhat different.

Since the oscillator may require a start-up time consid-

erably longer than the FSCM sample clock time, a false

clock failure may be detected. To prevent this, the

internal oscillator block is automatically configured as

the device clock and functions until the primary clock is

stable (the OST timer has timed out). This is identical

to Two-Speed Start-up mode. Once the primary clock is

stable, the INTRC returns to its role as the FSCM

source.

As noted in Section 20.4.1 “Special Considerations

for Using Two-Speed Start-up”, it is also possible to

select another clock configuration and enter an alternate

power-managed mode while waiting for the primary

clock to become stable. When the new power-managed

mode is selected, the primary clock is disabled.

OSCFIF

CM Output

Device

Clock

Output

Sample Clock

Failure

Detected

Oscillator

Failure

Note:

The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

(Q)

CM Test

Note:

The same logic that prevents false oscilla-

tor failure interrupts on POR, or wake from

Sleep, will also prevent the detection of

the oscillator’s failure to start at all

following these events. This can be

avoided by monitoring the OSTS bit and

using a timing routine to determine if the

oscillator is taking too long to start. Even

so, no oscillator failure interrupt will be

flagged.

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