XRT79L71IB datasheet(71/109 Pages) EXAR

71 / 109 page

XRT79L71

REV. 1.0.0

1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

• To detect and flag B1 byte errors

• To detect and flag PLCP FEBE/REI events

• To extract out the payload data from incoming PLCP frame (which consists of ATM cells) and to route this

data to the Receive ATM Cell Processor block for further processing

• Can be by-passed for Direct-Mapped ATM Applications

The Receive LAPD Controller Block

The purpose of the Receive LAPD Controller block is to permit the user to receive LAPD/PMDL (Path

Maintenance Data Link) Messages from the remote terminal equipment. The Receive LAPD Controller block

comes with a Receive LAPD Controller (not to be confused with the Receive High-Speed HDLC Controller

block) and 90 bytes of on-chip RAM (for storage of inbound PMDL Messages) after reception.

The Receive SSM Controller Block (E3, ITU-T G.832 Applications Only)

The Receive Trail-Trace Message Controller Block (E3, ITU-T G.832 Applications Only)

The Receive FEAC Controller Block (DS3, C-bit Parity Applications Only)

The purpose of the Receive FEAC Controller block is to permit the user to receive FEAC (Far-End Alarm &

Control) Messages from the remote terminal equipment.

NOTE: The Receive FEAC Controller block is only active if the XRT79L71 is configured to operate in the DS3, C-bit Parity

Framing format.

The Receive ATM Cell Processor Block

The purpose of the Receive ATM Cell Processor block is to extract out the data (being carried by the incoming

DS3/E3 frame or PLCP frame data-stream) and to perform the following operations on it.

• Cell Delineation

• HEC Byte Verification

• User and Idle Cell Filtering

• To receive cells with user-specified header bytes and to load them into the Receive Cell Extraction Memory

Buffer (where they can be read out and accessed via the Microprocessor Interface)

• To read out a user-specified ATM cell (which is residing in the Receive Cell Insertion Buffer) and to insert this

cell into the Receive ATM Cell traffic

• To route all filtered cells to the RxFIFO (where it will be made available to the ATM Layer Processor via the

Receive UTOPIA Interface block)

The Receive Overhead Data Output Interface block

The purpose of the Receive Overhead Data Output Interface block is to permit the user to extract out the

overhead bits (within the incoming DS3/E3 data-stream) and to route this data to some off-chip System-Side

Terminal Equipment circuitry.

The Receive UTOPIA Interface block

The purpose of the Receive UTOPIA Interface block is to provide a standard UTOPIA Level 1, 2 or 3 interface

to the ATM Layer Processor, for reading out the contents of all ATM cells that are written into the RxFIFO.

The Receive UTOPIA Interface block can be configured to operate with either an 8 or 16-bit wide Receive

UTOPIA Data bus.

NOTE: The Receive UTOPIA Interface block supports UTOPIA Level 3 from a signaling stand-point. The Receive UTOPIA

Interface block (within the XRT79L71) still only supports a 16-bit wide (not 32-bit wide) UTOPIA Bus and only

operates up to 50MHz (not 100MHz).

A MORE DETAILED FUNCTIONAL/ARCHITECTURAL DESCRIPTION FOR THE ATM UNI MODE

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