XRT79L71IB datasheet(22/109 Pages) EXAR

22 / 109 page

XRT79L71

1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

REV. 1.0.0

TxNibClk/

TxGFCMSB/

SendFCS

I/O

Transmit Nibble Clock Output pin/Transmit GFC Byte - MSB Indicator Out-

put/Send FCS Value Request Input:

The function of this input/output pin depends upon whether the XRT79L71 is

configured to operate in the Clear-Channel Framer Mode, the High-Speed HDLC

Controller Mode or in the ATM Mode.

Clear-Channel Framer Mode - TxNibClk - Transmit Nibble Clock Output pin:

When operating in the Nibble-Parallel Mode the XRT79L71 will derive this clock

signal from either the TxInClk or the RxLineClk signal depending upon whether

the chip is operating in the Local-Timing or Loop-Timing Mode.

The user is advised to configure the Terminal Equipment to output the outbound

payload data to the XRT79L71 onto the TxNib_[3:0] input pins, upon the rising

edge of this clock signal. The Transmit Payload Data Input Interface block will

sample the data, residing on the TxNib_[3:0] line, upon the falling edge this clock

signal.

NOTES:

For DS3 applications, the XRT79L71 will output 1176 clock pulses to

the System-Side terminal equipment for each outbound DS3 frame.

For E3, ITU-T G.832 applications, the XRT79L71 will output 1074 clock

pulses to the System-Side terminal equipment for each outbound E3

frame.

For E3, ITU-T G.751 applications, the XRT79L71 will output 384 clock

pulses to the System-Side terminal equipment for each outbound E3

frame.

ATM Mode - TxGFCMSB - Transmit GFC Input Port - MSB Indicator Output:

This signal, along with TxGFC and TxGFCClk combine to function as the Trans-

mit GFC Nibble Field serial input port. This output signal will pulse "High" when

the MSB (most significant bit) of the GFC nibble for a given outbound cell is

expected at the TxGFC input pin.

High-Speed HDLC Controller Mode - SendFCS - Transmit High-Speed

HDLC Controller - Send FCS Command Input pin:

The System-Side terminal equipment is expected to control both this input pin,

along with the SendMSG input pin, during the construction and transmission of

each outbound HDLC frame.

This input pin is used to command the Transmit HDLC Controller block to com-

pute and insert the computed FCS (Frame-Check Sequence) value into the

back-end of the outbound HDLC frame, as a trailer.

If the user has configured the Transmit HDLC Controller block to compute and

insert a CRC-16 value into the outbound HDLC frame, then the System-Side ter-

minal equipment is expected to hold this input pin "High" for two periods of TxH-

DLCClk.Conversely, if the user has configured the Transmit HDLC Controller

block to compute and insert a CRC-32 value into the outbound HDLC frame,

then the System-Side terminal equipment is expected to hold this input pin

"High" for four (4) periods of TxHDLCClk.

NOTES:

This input/output pin is inactive if the XRT79L71 has been configured to

operate in the PPP Mode.

This input/output pin is inactive if the XRT79L71 has been configured to

operate in the Clear-Channel Framer/Serial mode.

PIN #NAME

TYPE

DESCRIPTION

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