MC68HC908GR4MP datasheet(240/286 Pages) FREESCALE

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Timer Interface Module (TIM)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

240

Freescale Semiconductor

22.9.2 TIM Counter Registers

The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter.

Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent

reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter

registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.

NOTE

If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by

reading TCNTL before exiting the break interrupt. Otherwise, TCNTL

retains the value latched during the break.

Table 22-2. Prescaler Selection

PS2–PS0

TIM Clock Source

000

Internal bus clock

÷1

001

Internal bus clock

÷ 2

010

Internal bus clock

÷ 4

011

Internal bus clock

÷ 8

100

Internal bus clock

÷ 16

101

Internal bus clock

÷ 32

110

Internal bus clock

÷ 64

111

Not available

Address:

T1CNTH, $0021 and T2CNTH, $002C

Bit 7

654321

Bit 0

Read:

Bit 15

Bit 8

Write:

Reset:

00000000

= Unimplemented

Figure 22-5. TIM Counter Registers High (TCNTH)

Address:

T1CNTL, $0022 and T2CNTL, $002D

Bit 7

654321

Bit 0

Read:

Bit 7

654321

Bit 0

Write:

Reset:

00000000

= Unimplemented

Figure 22-6. TIM Counter Registers Low (TCNTL)

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