AMD-K6-2ESLASH233AMZ datasheet(128/332 Pages) AMD

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110

Signal Descriptions

Chapter 5

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

5.30

INTR (Maskable Interrupt)

Pin Attribute

Input

Pin Location

AD-34

Summary

INTR is the system’s maskable interrupt input to the processor.

When the processor samples and recognizes INTR asserted, the

processor executes a pair of interrupt acknowledge bus cycles

and then jumps to the interrupt service routine specified by the

interrupt number that was returned during the interrupt

acknowledge sequence. The processor only recognizes INTR if

the interrupt flag (IF) in the EFLAGS register equals 1.

Sampled

The processor samples INTR as a level-sensitive input on every

clock edge, but the interrupt request is not recognized until the

next instruction boundary. The system logic can drive INTR

either synchronously or asynchronously. If it is asserted

asynchronously, it must be asserted for a minimum pulse width

of two clocks. In order to be recognized, INTR must remain

asserted until an interrupt acknowledge sequence is complete.

5.31

INV (Invalidation Request)

Pin Attribute

Input

Pin Location

U-05

Summary

During an inquire cycle, the state of INV determines whether

an addressed cache line that is found in the processor’s

instruction or data cache transitions to the invalid state or the

shared state.

If INV is sampled asserted during an inquire cycle, the

processor transitions the cache line (if found) to the invalid

state, regardless of its previous state. If INV is sampled negated

during an inquire cycle, the processor transitions the cache line

(if found) to the shared state. In either case, if the cache line is

found in the modified state, the processor writes it back to

memory before changing its state.

Sampled

INV is sampled on the clock edge on which EADS# is sampled

asserted.

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