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AMD-K6-2E/233AMZ bảng dữ liệu(PDF) 17 Page - Advanced Micro Devices |
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AMD-K6-2E/233AMZ bảng dữ liệu(HTML) 17 Page - Advanced Micro Devices |
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17 / 332 page ![]() About this Data Sheet xvii 22529B/0—January 2000 AMD-K6™-2E Processor Data Sheet Preliminary Information About this Data Sheet The AMD-K6™-2E Processor Data Sheet is the complete specification of the AMD-K6-2E embedded processor. Overview This data sheet is organized into the following sections: Chapter 1, “AMD-K6™-2E Processor” on page 1, provides a list of the AMD-K6-2E processor’s distinguishing characteristics, a description of the key features, and a discussion about the Super7™ platform initiative. Chapter 2, “Internal Architecture” on page 7, describes the functional elements of the advanced design techniques, known as the RISC86® microarchitecture, implemented by the AMD-K6-2E processor. Chapter 3, “Software Environment” on page 23, provides a general overview of the AMD-K6-2E processor’s x86 software environment and briefly describes the data types, registers, operating modes, interrupts, and instructions supported by the AMD-K6-2E processor’s architecture and design implementation. Chapter 4, “Logic Symbol Diagram” on page 83, contains the AMD-K6-2E processor logic symbol diagram. Chapter 5, “Signal Descriptions” on page 85, lists the signals and their descriptions alphabetically and by function. Chapter 6, “Bus Cycles” on page 133, describes and illustrates the timing and relationship of bus signals during various types of bus cycles. Chapter 7, “Power-On Configuration and Initialization” on page 179, describes how the system logic resets the AMD-K6-2E processor using the RESET signal. Chapter 8, “Cache Organization” on page 185, describes the basic architecture and resources of the AMD-K6-2E processor’s internal caches. Chapter 9, “Write Merge Buffer” on page 205, describes the 8-byte write merge buffer and how merging multiple write cycles into a single write cycle ultimately increases overall system performance. Chapter 10, “Floating-Point and Multimedia Execution Units” on page 213, describes the AMD-K6-2E processor’s IEEE 754-compatible and 854-compatible floating point |
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