AMD-K6-2ESLASH233AMZ datasheet(63/332 Pages) AMD

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Chapter 3

Software Environment

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

UC/WC Cacheability

Control Register

(UWCCR)

The AMD-K6-2E processor provides two variable-range Memory

Type Range Registers (MTRRs)—MTRR0 and MTRR1—that

each specify a range of memory. Each range can be defined as

uncacheable (UC) or write-combining (WC) memory. Figure 37

shows the format of the UWCCR register. For more detailed

information about the MTRR0, MTRR1, and UWCCR registers,

see “Memory Type Range Registers” on page 207.

Figure 37. UC/WC Cacheability Control Register (UWCCR)

Processor State

Observability

The AMD-K6-2E processor provides the processor state

observability register (PSOR) (see Figure 38).

Figure 38. Processor State Observability Register (PSOR)

Physical Address Mask 0

Physical Base Address 0

Physical Address Mask 1

Physical Base Address 1

MTRR1

MTRR0

Symbol

Description

Bits

UC0

Uncacheable Memory Type

WC0

Write-Combining Memory Type

Symbol

Description

Bits

UC1

Uncacheable Memory Type

WC1

Write-Combining Memory Type

Symbol

Description

Bit

NOL2

No L2 Functionality

STEP

Processor Stepping

7-4

Bus Frequency Divisor

2-0

STEP

Reserved

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