AMD-K6-2ESLASH233AMZ datasheet(174/332 Pages) AMD

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156

Bus Cycles

Chapter 6

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

AHOLD-Initiated

Inquire Hit to Shared

or Exclusive Line

In Figure 62, the processor asserts HIT# and negates HITM# off

the clock edge after the clock edge on which EADS# is sampled

asserted, indicating the current inquire cycle hits either a

shared or exclusive line. (HIT# is driven in the same state until

the next inquire cycle.) The processor samples INV asserted

during the inquire cycle and transitions the line to the Invalid

state regardless of its previous state.

During an AHOLD-initiated inquire cycle, the processor

samples AHOLD on every clock edge until it is negated. In

Figure 62, the processor asserts ADS# off the same clock on

which AHOLD is sampled negated. If the inquire cycle hits a

modified line, the processor performs a writeback cycle before

it drives a new bus cycle. The next section describes the

AHOLD-initiated inquire cycle that hits a modified line.

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