AMD-K6-2ESLASH233AMZ datasheet(170/332 Pages) AMD

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152

Bus Cycles

Chapter 6

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

HOLD-Initiated

Inquire Hit to

Modified Line

Figure 60 on page 153 shows the same sequence as Figure 59,

but in Figure 60, the inquire cycle hits a modified line and the

processor asserts both HIT# and HITM#. In this example, the

processor performs a writeback cycle immediately after the

inquire cycle. It updates the modified cache line to the external

memory (normally, external cache or DRAM). The processor

uses the address (A[31:5]) that was latched during the inquire

cycle to perform the writeback cycle. The processor asserts

HITM# throughout the writeback cycle and negates HITM# one

clock edge after the last expected BRDY# of the writeback is

sampled asserted.

When the processor samples EADS# during the inquire cycle, it

also samples INV to determine the cache line MESI state after

the inquire cycle. If INV is sampled asserted during an inquire

cycle, the processor transitions the line (if found) to the Invalid

stat e, regardless of its prev ious sta te. Th e c a ch e line

invalidation operation is not visible on the bus. If INV is

sampled negated during an inquire cycle, the processor

transitions the line (if found) to the Shared state. In Figure 60

the processor samples INV asserted during the inquire cycle.

In a HOLD-initiated inquire cycle, the system logic can negate

HOLD off the same clock edge on which EADS# is sampled

asserted. The processor drives HIT# and HITM# on the clock

edge after the clock edge on which EADS# is sampled asserted.

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