AMD-K6-2ESLASH233AMZ datasheet(176/332 Pages) AMD

176 / 332 page

158

Bus Cycles

Chapter 6

AMD-K6™-2E Processor Data Sheet

22529B/0—January 2000

Preliminary Information

AHOLD-Initiated

Inquire Hit to

Modified Line

Figure 63 on page 159 shows an AHOLD-initiated inquire cycle

that hits a modified line. During the inquire cycle in this

example, the processor asserts both HIT# and HITM# on the

clock edge after the clock edge that it samples EADS# asserted.

This condition indicates that the cache line exists in the

processor’s data cache in the Modified state.

If the inquire cycle hits a modified line, the processor performs

a writeback cycle immediately after the inquire cycle to update

the modified cache line to shared memory (normally external

cache or DRAM). In Figure 63, the system logic holds AHOLD

asserted throughout the inquire cycle and the processor

writeback cycle. In this case, the processor is not driving the

address bus during the writeback cycle because AHOLD is

sampled asserted. The system logic writes the data to memory

by using its latched copy of the inquire cycle address. If the

processor samples AHOLD negated before it performs the

writeback cycle, it drives the writeback cycle by using the

address (A[31:5]) that it latched during the inquire cycle.

If INV is sampled asserted during an inquire cycle, the

processor transitions the line (if found) to the Invalid state,

regardless of its previous state (the cache invalidation

operation is not visible on the bus). If INV is sampled negated

during an inquire cycle, the processor transitions the line (if

found) to the Shared state. In either case, if the line is found in

the Modified state, the processor writes it back to memory

before changing its state. Figure 63 shows that the processor

samples INV asserted during the inquire cycle and invalidates

the cache line after the inquire cycle.

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