CC1110-RTR1 datasheet(109/203 Pages) TI

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CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 109 of 202

13.6.3 Channel Mode Control

The channel modes for each channel are set

by the control and status registers TxCCTLn,

where n is the channel number, 0 or 1. The

settings include input capture and output

compare modes.

13.6.4 Input Capture Mode

When the channel is configured as an input

capture channel, the I/O pin associated with

that channel is configured as an input. After

the timer has been started, either a rising

edge, falling edge or any edge on the input pin

triggers a capture of the 8-bit counter contents

into the associated capture register. Thus the

timer is able to capture the time when an

external event takes place.

The channel input pins are synchronized to the

internal system clock. Thus pulses on the input

pins must have a minimum duration greater

than the system clock period.

Note: before an input/output pin can be used

by the timer, the required I/O pin must be

configured as a Timer 3/4 peripheral pin as

described in sections 13.1.4.4 and 13.1.4.5.

The contents of the 8-bit capture registers, is

read out from registers TxCCn.

When a capture takes place the interrupt flag

corresponding to the actual channel is set.

This interrupt flag is TIMIF.TxCHnIF. An

interrupt

request

generated

the

corresponding interrupt mask bit TxCCTLn.IM

is set.

13.6.5 Output Compare Mode

In output compare mode the I/O pin associated

with a channel should be configured as an

output. After the timer has been started, the

contents of the counter is compared with the

contents of the channel compare register

TxCCn. If the compare register equals the

counter contents, the output pin is set, reset or

toggled according to the compare output mode

setting of TxCCTL.CMP1:0. Note that all

edges on output pins are glitch-free when

operating in a given compare output mode.

For simple PWM use, output compare modes

4 and 5 are preferred.

Writing to the compare register TxCC0 does

not take effect on the output compare value

until the counter value is 0x00. Writing to the

compare

TxCC1

takes

effect

immediately.

When a compare occurs the interrupt flag

corresponding to the actual channel is set.

This interrupt flag is TIMIF.TxCHnIF. An

interrupt

request

generated

the

corresponding interrupt mask bit TxCCTLn.IM

is set.

13.6.6 Timer 3 and 4 interrupts

There is one interrupt vector assigned to each

of the timers. These are T3IF (interrupt 11)

and T4IF (interrupt 12). An interrupt request is

generated when one of the following timer

events occur:

•

Counter reaches terminal count value.

•

Input capture event.

•

Output compare event

The SFR register TIMIF contains all interrupt

flags for Timer 3 and Timer 4. The register bits

TIMIF.TxOVFIF

and

TIMIF.TxCHnIF

contain the interrupt flags for the two terminal

count value events and the four channel

compare/capture events, respectively. An

interrupt request is only generated when the

corresponding interrupt mask bit is set. If there

are

other

pending

interrupts,

the

corresponding interrupt flag must be cleared

by the CPU before a new interrupt request can

be generated. Also, enabling an interrupt mask

bit will generate a new interrupt request if the

corresponding interrupt flag is set.

13.6.7 Timer 3 and Timer 4 DMA triggers

There are two DMA triggers associated with

Timer 3 and two DMA triggers associated with

Timer 4. These are the following:

•

T3_CH0 : Timer 3 channel 0 compare

•

T3_CH1 : Timer 3 channel 1 compare

•

T4_CH0 : Timer 4 channel 0 compare

•

T4_CH0 : Timer 4 channel 1 compare

Refer to section 13.2 on page 78, for a

description on use of DMA channels.

13.6.8 Timer 3 and 4 registers

The Timer 3 and 4 registers are described on

the following pages.

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