CC1110-RTR1 datasheet(56/203 Pages) TI

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CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 56 of 202

on the bi-directional Debug Data pin at the

positive edge of Debug Clock and data is

sampled on the negative edge of this clock.

Debug commands are sent by an external host

and consist of 1 to 4 output bytes (including

command byte) from the host and an optional

input byte read by the host. Figure 9 shows a

timing diagram of data on the debug interface.

The first byte of the debug command is a

command byte and is encoded as follows:

•

bits 7 to 3 : instruction code

•

bit 2

: return input byte to host

when high

•

bits 1 to 0 : number of output bytes from

host following instruction code byte

P2_2

P2_1

command

first data byte

second data byte

host input byte

Figure 9: Debug interface timing diagram

12.9.3 Debug Commands

The debug commands are shown in Table 33.

Some of the debug commands are described

in further detail in the following sections

12.9.4 Debug Lock Bit

For software code security, the Debug

Interface may be locked. When the Debug

Lock bit , DBGLOCK, is set (see section 13.14.3)

all debug commands except CHIP_ERASE,

READ_STATUS

and

GET_CHIP_ID

are

disabled and will not function.

The CHIP_ERASE command is used to clear

the Debug Lock bit.

12.9.5 Debug Configuration

The

commands

WR_CONFIG

and

RD_CONFIG are used to access the debug

configuration data byte. The format and

description of this configuration data is shown

in Table 34.

12.9.6 Debug Status

A Debug status byte is read using the

READ_STATUS command. The format and

description of this debug status is shown in

Table 35.

The READ_STATUS command is used e.g. for

polling the status of flash chip erase after a

CHIP_ERASE command or oscillator stable

status required for debug commands HALT,

RESUME, DEBUG_INSTR, STEP_REPLACE

and STEP_INSTR.

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