CC1110-RTR1 datasheet(58/203 Pages) TI

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CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 58 of 202

Bit

Name

Description

Flash chip erase done

0 Chip erase in progress

chip_erase_done

1 Chip erase done

PCON idle

0 CPU is running

pcon_idle

1 CPU is idle (clock gated)

CPU halted

0 CPU running

cpu_halted

1 CPU halted

Power Mode 0

0 Power Mode 1-3 selected

power_mode_0

1 Power Mode 0 selected

Halt status. Returns cause of last CPU halt

0 CPU was halted by HALT debug command

halt_status

1 CPU was halted by software or hardware breakpoint

Debug locked. Returns value of DBGLOCK bit

0 Debug interface is not locked

debug_locked

1 Debug interface is locked

Oscillators stable. This bit represents the status of the

CLKCON.XSOC_STB and CLKCON.HFRC_STB register bits.

0 Oscillators not stable

oscillator_stable

1 Oscillators stable

Stack overflow. This bit indicates when the CPU writes to

DATA memory space at address 0xFF which is possibly a

stack overflow

0 No stack overflow

stack_overflow

1 Stack overflow

Table 35: Debug Status

12.9.7 Hardware Breakpoints

The debug command SET_HW_BRKPNT

is used to set a hardware breakpoint. The

CC1110 supports up to four hardware

breakpoints. When a hardware breakpoint

is enabled, it will compare the CPU

address bus with the breakpoint.. When a

match occurs, the CPU is halted.

When issuing the SET_HW_BRKPNT, the

external host must supply three data bytes

that define the hardware breakpoint. The

hardware breakpoint itself consists of 18

bits while three bits are used for control

purposes. The format of the three data

bytes

for

the

SET_HW_BRKPNT

command is as follows.

The first data byte consists of the

following:

•

bits 7-5

: unused

•

bits 4-3

: breakpoint number; 0-3

•

bit 2

: 1=enable, 0=disable

•

bits 1-0

: Memory bank bits. Bits

17-16 of hardware breakpoint.

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