CC1110-RTR1 datasheet(82/203 Pages) TI

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CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 82 of 202

which the CPU is notified and the DMA

channel is rearmed.

13.2.2.8 DMA Priority

A DMA priority is associated with each DMA

access port and is configurable for each DMA

channel. The DMA priority is used to

determine the winner in the case of multiple

simultaneous internal memory requests, and

whether the DMA memory access should have

priority or not over a simultaneous CPU

memory access. In case of an internal tie, a

round-robin scheme is used to ensure access

for all. There are three levels of DMA priority:

High

. Highest internal priority. DMA access

will always prevail over CPU access.

Normal

. Second highest internal priority.

Guarantees that DMA access prevails over

CPU on at least every second try.

Low

. Lowest internal priority. DMA access will

always defer to a CPU access.

13.2.2.9 Byte or Word transfers

Determines whether 8-bit (byte) or 16-bit

(word) are done.

13.2.2.10 Interrupt mask

Upon completing a DMA transfer, the channel

can generate an interrupt to the processor.

This bit will mask the interrupt.

13.2.2.11 Mode 8 setting

This field determines whether to use seven or

8 bits of length byte for transfer length. Only

applicable when doing byte transfers.

13.2.3 DMA Configuration Setup

The DMA channel parameters such as

address mode, transfer mode and priority

described in the previous section have to be

configured before a DMA channel can be

armed and activated. The parameters are not

configured directly through SFR registers, but

instead they are written in a special DMA

configuration data structure in memory. Each

DMA channel in use requires its own DMA

configuration

data

structure.

The

DMA

configuration data structure consists of eight

bytes and is described in section 13.2.6 A

DMA configuration data structure may reside

at any location decided upon by the user

software, and the address location is passed

to the DMA controller through a set of SFRs

DMAxCFGH:DMAxCFGL, Once a channel has

been armed, the DMA controller will read the

configuration data structure for that channel,

given

the

address

DMAxCFGH:DMAxCFGL.

It is important to note that the method for

specifying the start address for the DMA

configuration data structure differs between

DMA channel 0 and DMA channels 1-4 as

follows:

DMA0CFGH:DMA0CFGL gives the start address

for

DMA

channel

configuration

data

structure.

DMA1CFGH:DMA1CFGL gives the start address

for DMA channel 1 configuration data structure

followed by channel 2-4 configuration data

structures.

Thus the DMA controller expects the DMA

configuration

data

structures

for

DMA

channels 1-4 to lie in a contiguous area in

memory, starting at the address held in

DMA1CFGH:DMA1CFGL and consisting of 32

bytes.

13.2.4 Stopping DMA Transfers

Ongoing DMA transfer or armed DMA

channels will be aborted using the DMAARM

One or more DMA channels are aborted by

writing the following to the DMAARM register.

•

Writing a 1 to DMAARM.ABORT, and at

the same time,

•

Select which DMA channels to abort by

setting

the

corresponding,

DMAARM.DMAARMx bits.

An example of DMA channel arm and disarm

is shown in Figure 12.

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