CC1110-RTR1 datasheet(49/203 Pages) TI

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CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 49 of 202

IEN2 (0x9A) – Interrupt Enable 2 Register

Bit

Name

Reset

R/W

Description

7:6

Not used. Read as 0

WDTIE – Watchdog timer interrupt enable

Interrupt disabled

WDTIE

R/W

Interrupt enabled

P1IE – Port 1 interrupt enable

Interrupt disabled

P1IE

R/W

Interrupt enabled

UTX1IE – USART1 TX interrupt enable

Interrupt disabled

UTX1IE

R/W

Interrupt enabled

UTX0IE - USART0 TX interrupt enable

Interrupt disabled

UTX0IE

R/W

Interrupt enabled

P2IE – Port 2 interrupt enable

Interrupt disabled

P2IE

R/W

Interrupt enabled

RFIE – RF general interrupt enable

Interrupt disabled

RFIE

R/W

Interrupt enabled

12.7.2 Interrupt Processing

When an interrupt occurs, the CPU will vector

to the interrupt vector address as shown in

Table 29. Once an interrupt service has

begun, it can be interrupted only by a higher

priority interrupt. The interrupt service is

terminated by a RETI return from interrupt

instruction. When a RETI is performed, the

CPU will return to the instruction that would

have been next when the interrupt occurred.

When the interrupt condition occurs, the CPU

will also indicate this by setting an interrupt

flag bit in the interrupt flag registers. This bit is

set regardless of whether the interrupt is

enabled or disabled. If the interrupt is enabled

when an interrupt flag is set, then on the next

instruction

cycle

the

interrupt

will

acknowledged by hardware forcing an LCALL

to the appropriate vector address.

Interrupt response will require a varying

amount of time depending on the state of the

CPU when the interrupt occurs. If the CPU is

performing an interrupt service with equal or

greater priority, the new interrupt will be

pending until it becomes the interrupt with

highest priority. In other cases, the response

time depends on current instruction. The

fastest possible response to an interrupt is

seven instruction cycles. This includes one

instruction cycle for detecting the interrupt and

six cycles to perform the LCALL.

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