CC1110-RTR1 datasheet(59/203 Pages) TI

59 / 203 page

CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 59 of 202

The second data byte consists of bits 15-8

of the hardware breakpoint.

The third data byte consists of bits 7-0 of

the hardware breakpoint.

12.9.8 Flash Programming

Programming of the on-chip flash is

performed via the debug interface. The

external

host

must

initially

send

instructions using the DEBUG_INSTR

debug command to perform the flash

programming with the Flash Controller as

described in section 13.14 on page 147.

12.10 RAM

The

CC1110 contains static RAM. At power-

on the contents of RAM is undefined. The

RAM size is 4 KB in total. The RAM retains

data in all power modes.

The memory locations 0xFDAA-0xFEFF

consisting of 342 bytes in XDATA memory

do not retain data when power modes

PM2/3 is entered.

12.11 Flash Memory

The on-chip flash memory consists of

32768 bytes. The flash memory is

primarily intended to hold program code.

The flash memory has the following

features:

•

Flash page erase time: 20 ms

•

Flash chip (mass) erase time: 20 ms

•

Flash write time: 20 µs

•

Data retention

1:100 years

•

Program/erase

endurance:

1,000

cycles

The flash memory consists of the Flash

Main Page which is where the CPU reads

program code and data. The flash memory

also contains a Flash Information Page

which contains the Flash Lock Bits. The

Flash Information Page and hence the

Lock Bits is only accessed by first

selecting this page through the Debug

Interface. The Flash Controller (see

section 13.14) is used to write and erase

the contents of the flash memory.

When the CPU reads instructions from

flash

memory,

fetches

the

instruction

through

cache.

The

instruction cache is provided mainly to

reduce power consumption by reducing

the amount of time the flash memory itself

is accessed. The use of the instruction

cache

may

disabled

with

the

MEMCTR.CACHDIS register bit.

12.12 Memory Arbiter

The

CC1110 includes a memory arbiter

which handles CPU and DMA access to all

memory space.

A control register MEMCTR is used to

control various aspects of the memory

sub-system. The MEMCTR register is

described in the following.

1 At room temperature

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