CC1110-RTR1 datasheet(63/203 Pages) TI

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CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 63 of 202

Table 36: Peripheral I/O Pin Mapping

Periphery /

Function

ADC

USART0 Alt 1

SPI

Alt. 2

USART0 Alt. 1

UART

Alt. 2

USART1 Alt.1

SPI

Alt. 2

USART1 Alt. 1

UART Alt. 2

TIMER1 Alt.1

Alt. 2

TIMER3 Alt.1

Alt. 2

TIMER4 Alt.1

Alt. 2

32.768kHz

XOSC

DEBUG

13.1.4.1 USART0

The SFR register bit PERCFG.U0CFG selects

whether to use alternative 1 or alternative 2

locations.

In Table 36, the USART0 signals are shown as

follows:

UART:

•

RX : RXDATA

•

TX : TXDATA

•

RT : RTS

•

CT : CTS

SPI:

•

MI : MISO

•

MO : MOSI

•

C : SCK

•

SS : SSN

P2DIR.PRIP0

selects

the

order

precedence

when

assigning

several

peripherals to port 0, i.e. the situation when

several peripherals are assigned to the same

pin locations. When set to 00, USART0 has

precedence. Note that if UART mode is

selected and hardware flow control is disabled,

USART1 or timer 1 will have precedence to

use ports P0_4 and P0_5.

P2SEL.PRI3P1 and P2SEL.PRI0P1 select

the order of precedence when assigning

several peripherals to port 1. USART0 has

precedence when both are set to 0. Note that if

UART mode is selected and hardware flow

control is disabled, timer 1 or timer 3 will have

precedence to use ports P1_2 and P1_3.

13.1.4.2 USART1

The SFR register bit PERCFG.U1CFG selects

whether to use alternative 1 or alternative 2

locations.

In Table 36, the USART1 signals are shown as

follows:

•

RX : RXDATA

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